Simulation Study of a Low ON-State Voltage Superjunction IGBT With Self-Biased PMOS

Abstract

In this brief, a novel superjunction (SJ)-insulated-gate bipolar transistor (SJ-IGBT) is proposed and investigated by simulation, where a floating N-base region on the P-pillar region is introduced to form a self-biased PMOS. In the on-state, the PMOS can increase the hole quasi-Fermi potential of the P-pillar region, enhancing the carrier-storage effect in the N-pillar and P-pillar regions and reducing the on-state voltage consequently. In the turn-off transient, because the PMOS can be automatically turned on as a consequence of the potential rise of the P-pillar region with hole accumulation, the proposed SJ-IGBT can be rapidly turned off. The results from TCAD simulation reveal that the on-state voltage of the proposed SJ-IGBT is 46.7% lower than that of the conventional SJ-IGBT with P-pillar shorted with cathode (SJ-IGBT-A) and nearly equivalent to that of the conventional SJ-IGBT with gate on the P-pillar (SJ-IGBT-B). In addition, the off-state breakdown voltage of the proposed SJ-IGBT can roughly keep an identical value with that of SJ-IGBT-A and is 25% higher than that of SJ-IGBT-B. In addition, with the same VON of 1.16 V, the turn-off energy loss of the proposed device is 1.2 mJ/cm2, which is 94.7% lower than that of SJ-IGBT-A and 20% lower than that of SJ-IGBT-B.