Tunneling Leakage Current Research Articles

Modeling and Analysis of the Asymmetric Source/Drain Extension CMOS Transistors for Nanoscale Technologies

The asymmetric source/drain extension (ASDE) transistor can be a suitable option because of improved short channel effects in technology nodes beyond 32 nm. In this paper, we have analyzed the impact of asymmetric drain extension reduction on the device metrics, namely, gate-to-drain capacitance, drain current, subthreshold leakage, and gate tunneling leakage current. Also, analytical models have been developed to model the effect of the ASDE devices. Based on our proposed analytical model, SPICE-compatible transistor models have been developed to include the ASDE device structure as possible design options. With our SPICE-compatible transistor models, large-scale circuit simulation can be performed to evaluate the benefits and the overheads associated with the ASDE devices. It is observed from circuit simulations that there is an optimal drain extension length which is different from the source extension length. With the ASDE devices, the circuit power delay product can effectively be reduced by almost 35% with respect to the conventional symmetric devices.

Multi-layer high- κ interpoly dielectric for floating gate flash memory devices

We present a systematic simulation and experimental study of tunneling leakage current of the interpoly dielectric (IPD) layer in a floating gate (FG) type flash memory. IPD layers with different structural and material combinations such as HfLaO and 4% Tb-doped HfO 2 were studied. It is shown that compared with a conventional Al 2O 3–HfO 2–Al 2O 3 high–low–high barrier structure, the HfO 2–Al 2O 3–HfO 2 multilayer IPD stack with a low–high–low barrier structure has a lower leakage current due to the longer effective electron tunneling distance. Results also show that multilayer IPD structure has advantage of better thermal stability compared to the single layer IPD. Further work with simulations and experiments results suggest that the presence of a thin interfacial layer between polysilicon FG and IPD can increase the magnitude of leakage current by two or three orders. Nitridation of polysilicon floating gate reduced the leakage current by around two orders of magnitude at a constant equivalent oxide thickness. This is due to the elimination of the interfacial layer between polysilicon and high- κ IPD.

On Composite Leakage Current Maximization

Sub-threshold, gate and reverse biased junction band-to-band tunneling leakage currents depend on the logic inputs of a CMOS circuit. In this paper, we consider all leakage currents together and generate pattern with the objective of maximizing the overall leakage current to avoid any optimism in leakage current estimation. The computation involves Boolean reasoning on a pre-characterized set of interconnected gates. This problem is known to be computationally intractable. We propose a heuristic with reduced complexity by looking for a lower and an upper bound instead. The bounds tighten progressively with computation and converge asymptotically on a provably exact solution. By appropriately setting the objective function, the same algorithm may also be applied to find the pattern that minimizes the leakage power in the system idle state, which is considered to be ~50% of the total power consumed in the current technology generations.

Analysis of Scaling Strategies for Sub-30 nm Double-Gate SOI N-MOSFETs

State-of-the-art device simulation is applied to the analysis of possible scaling strategies for the future CMOS technology, adopting the ultrathin silicon body (UTB) double-gate (DG) MOSFET and considering the main figures of merit (FOM) for the high-performance N-MOS transistor. The results of our analysis confirm the potentials of UTB-DG MOSFETs. In particular, the possibility to control the short-channel effects by thinning the silicon layer is fully exploited allowing to adopt almost undoped silicon channel, leading to reduced transversal field. As a consequence, the impact of surface roughness at the Si-oxide interface and the gate tunneling leakage current are substantially reduced compared to the case of highly doped bulk MOSFETs. According to our results, thanks to the suppression of gate leakage current, scaling of the UTB-DG MOSFET down to the 32 nm technology node appears possible adopting -based gate dielectrics. In spite of the improved mobility at given inversion charge density, the simulated on-currents are substantially lower than those required by the 2005 ITRS for the 45 and 32 nm nodes . Nonetheless, thanks to relaxed scaling of the oxide thickness, hence to reduced gate capacitance, the requirements in terms of intrinsic delay and power-delay product can be satisfied. The issue of variability is analyzed by evaluating the dependence of the key FOM on the variation of critical dimensions such as the thickness of the gate oxide and of the silicon layer.

Direct tunneling stress-induced leakage current in ultrathin HfO2∕SiO2 gate dielectric stacks

The conduction mechanism(s) and behavior of direct tunneling stress-induced leakage current (SILC) through ultrathin hafnium oxide (HfO2)/silicon dioxide (SiO2) dual layer gate stack in metal-oxide-semiconductor (MOS) devices have been experimentally investigated in-depth. Both transient and steady-state SILCs have been studied after constant voltage stress (CVS) and constant current stress (CCS) in n-MOS capacitors with negative bias on the tantalum nitride (TaN) gate. The present report clearly indicates that the observed steady-state SILC is due to assisted tunneling via both monoenergetic trapped positive charges and neutral electron traps generated in the HfO2 layer during either CVS or CCS. SILC measured immediately after stress decays slowly due to tunnel detrapping of stress-induced trapped holes in the HfO2 layer. Furthermore, the mechanisms for stress-induced charge carrier generation/trapping and trap creation in the dielectric have been discussed. Our analysis also shows that CVS degrades the dielectric integrity more severely than CCS in the 4.2nm physically thick HfO2∕SiO2 stack.

High performance germanium MOSFETs

Ge is a very promising material as future channel materials for nanoscale MOSFETs due to its high mobility and thus a higher source injection velocity, which translates into higher drive current and smaller gate delay. However, for Ge to become main-stream, surface passivation and heterogeneous integration of crystalline Ge layers on Si must be achieved. We have demonstrated growth of fully relaxed smooth single crystal Ge layers on Si using a novel multi-step growth and hydrogen anneal process without any graded buffer SiGe layer. Surface passivation of Ge has been achieved with its native oxynitride (GeO x N y ) and high-permittivity (high-k) metal oxides of Al, Zr and Hf. High mobility MOSFETs have been demonstrated in bulk Ge with high-k gate dielectrics and metal gates. However, due to their smaller bandgap and higher dielectric constant, most high mobility materials suffer from large band-to-band tunneling (BTBT) leakage currents and worse short channel effects. We present novel, Si and Ge based heterostructure MOSFETs, which can significantly reduce the BTBT leakage currents while retaining high channel mobility, making them suitable for scaling into the sub-15 nm regime. Through full band Monte-Carlo, Poisson-Schrodinger and detailed BTBT simulations we show a dramatic reduction in BTBT and excellent electrostatic control of the channel, while maintaining very high drive currents in these highly scaled heterostructure DGFETs. Heterostructure MOSFETs with varying strained-Ge or SiGe thickness, Si cap thickness and Ge percentage were fabricated on bulk Si and SOI substrates. The ultra-thin (∼2 nm) strained-Ge channel heterostructure MOSFETs exhibited >4× mobility enhancements over bulk Si devices and >10× BTBT reduction over surface channel strained SiGe devices.

High Performance, Ultra-thin, Strained-Ge, Heterostructure FETs With High Mobility And Low Leakage

High mobility channel materials are very promising for enhanced transport in future nanoscale MOSFETs. However, because of their reduced bandgap, large Band-To-Band Tunneling (BTBT) leakage currents can ultimately limit the scalability of FETs incorporating high mobility (small bandgap) channels. For the first time, the tradeoffs between drive current (ION), intrinsic delay (τ), band-to-band tunneling (BTBT) leakage and short channel effects (SCE) have been systematically compared in futuristic high mobility materials, like strained-Si, strained-SiGe and relaxed-Ge. The optimal channel materials and device structures for nanoscale p-MOSFETs are discussed through detailed BTBT (including band structure and quantum effects), Full-Band Monte-Carlo, 1-D Poisson-Schrodinger simulations. We present a novel, Heterostructure FET, which can significantly reduce the off-state leakage currents, while retaining its high mobility, making it suitable for scaling into the sub-20nm regime. Through detailed experiments, we examine the enhanced transport and low leakage in ultra-thin, strained-Ge, heterostructure MOSFETs on bulk-Si and UT-SOI.

A method to calculate tunneling leakage currents in silicon inversion layers

This paper proposes a quantum mechanical model for the calculation of tunneling leakage currents in a metal-oxide-semiconductor structure. The model incorporates both variational calculus and the transfer matrix method to compute the subband energies and the lifetimes of the inversion layer states. The use of variational calculus simplifies the subband energy calculation due to the analytical form of the wave functions, which offers an attractive perspective towards the calculation of the electron mobility in the channel. The model can be extended to high-k dielectrics with several layers. Good agreement between experimental data and simulation results is obtained for metal gate capacitors.

Composition Dependence of Physical and Electrical Properties of HfSiON Films as Alternative Gate Dielectrics

Detailed investigation of the HfSiON electrical property dependence on Hf and N concentration has been conducted. The electrical property has been correlated with the film physical structure in this study. Increase in Hf and N concentrations enhances the film dielectric constant, especially when Hf-N bonds are formed in the film. The Hf-N formation results in the bandgap narrowing, leading to barrier height reduction at the same time. In view of the figure of merit in terms of the suppression of the direct tunneling leakage current, high Hf and N may be desirable for the application of HfSiON films as alternative gate dielectrics.

High-mobility low band-to-band-tunneling strained-Germanium double-gate heterostructure FETs: Simulations

Large band-to-band tunneling (BTBT) leakage currents can ultimately limit the scalability of high-mobility (small-bandgap) materials. This paper presents a novel heterostructure double-gate FET (DGFET) that can significantly reduce BTBT leakage currents while retaining its high mobility, making it suitable for scaling into the sub-20-nm regime. In particular, through one-dimensional Poisson-Schrodinger, full-band Monte Carlo, and detailed BTBT simulations, the tradeoffs between carrier transport, electrostatics, and BTBT leakage in high-mobility sub-20-nm Si-strained SiGe-Si (high germanium concentration) heterostructure PMOS DGFETs are thoroughly analyzed. The results show a dramatic (>100/spl times/) reduction in BTBT and an excellent electrostatic control of the channel while maintaining very high drive currents and switching frequencies in these nanoscale transistors.

Effect of gate-drain/source overlap on the noise in 90nm N-channel metal oxide semiconductor field effect transistors

In this paper, we have studied the effect of gate-drain/source overlap (LOV) on the drain channel noise and induced gate current noise (SIg) in 90nm N-channel metal oxide semiconductor field effect transistors using process and device simulations. As the change in overlap affects the gate tunneling leakage current, its effect on shot noise component of SIg has been taken into consideration. It has been shown that “control over LOV” allows us to get better noise performance from the device, i.e., it allows us to reduce noise figure, for a given leakage current constraint. LOV in the range of 0–10nm is recommended for the 90nm gate length transistors, in order to get the best performance in radio frequency applications.

High‐κ Dielectric Nanofilms Fabricated from Titania Nanosheets

In the semiconductor industry, increasing density requirements continue to motivate the production of microelectronic devices that function reproducibly at ever-smaller dimensions (a trend known as Moore’s law). The need for insulating films with nanometer-scale thickness that show good compatibility with semiconductor technology is a critical issue for future device development. As the film thickness scales down to 10 nm, conventional SiO2 gate dielectrics show a poorly insulating character with high leakage currents of 10– 10 A cm due to quantum tunneling, thereby causing large energy consumption and deteriorated device reliability. Continued device scaling will therefore require substitution of SiO2 with high-dielectric-constant (high-j) metal oxide gate dielectrics that afford high capacitance without reliance on film thickness, thus allowing for efficient charge injection and also reducing tunneling leakage currents. Here, we show that 2D titania (Ti0.87O2) nanosheets function as a high-j nanomaterial. We have successfully fabricated high-j nanofilms by forming multilayer assemblies of titania nanosheets via a layer-by-layer approach through solution-based processes at room temperature. The use of an atomically flat (001) SrRuO3 (SRO) epitaxial film as the bottom electrode enables the fabrication of atomically uniform, highly dense, and void-free nanofilms that retain the superior electrical properties of the titania nanosheets. These films exhibit a reduced leakage current density (10–10 A cm) with a high relative dielectric constant of ∼ 125, even for thicknesses as low as 10 nm. These results, as well as the facile molecular-scale assembly of the nanostructures, suggest that titania nanosheets are attractive candidates for use in nanocomponent insulating high-j dielectric films. In the area of high-j dielectrics, there is currently an intense research effort focused on the synthesis and device integration of various oxide materials. Current candidates are placed into two categories according to the j value: simple metal oxides with j= ∼ 10–20, such as Ta2O5, HfO2 and ZrO2, and materials with j> 100, such as rutile-type TiO2 [7] and (Ba,Sr)TiO3 (BST). [8] In addition to intrinsic properties such as a high dielectric constant and good insulating properties, high-j gate oxides have to fulfill a number of other requirements for device integration: i) they must be chemically stable in contact with the bottom electrodes (Si and/or metals), ii) for optimal performance, they should have an atomically defined interface with the bottom electrodes, without a low-j interfacial layer, and iii) they should have a simple metal oxide system and be accessible through a low temperature ( 600 °C), which often causes both a reduction in the polarizability due to non-stoichiometry, as well as degradation of the bottom electrode. Thus, the development of new high-j oxides fulfilling these requirements represents a critical challenge for materials science. In searching for alternative materials, we have focused on titania (Ti0.87O2) nanosheets, [4] a new class of nanomaterials that represent a modification of nanometer-sized titanium oxide prepared by delaminating layered titanates into their molecular single sheets (Fig. 1a). Compared with rutile and other high-j oxides, titania nanosheets have some unique features: i) they are completely 2D nanomaterials, with a thickness of 0.7 nm, and ii) due to their colloidal and negatively charged character, they can be self-assembled layer-by-layer via a solution-based process to construct ultrathin films. Therefore, the use of titania nanosheets as building blocks for high-j films could provide a potential route to the room-temperature manufacture of high-j devices, eliminating the degradation of the bottom electrode during the annealing process. Here, we report the performance of high-j nanofilms fabricated from titania nanosheets by a solution-based layer-by-layer approach. Multilayer films of large-sized titania nanosheets (with an average lateral size of 30 lm) have been fabricated by an electrostatic self-assembly technique, using poly(diallyldimethylammonium) (PDDA) as a counter polycation. As the bottom electrode, we use an atomically flat conducting SRO substrate, consisting of a 50 nm thick (001)-oriented epitaxial SRO layer on a (001) SrTiO3 single crystal. The as-deC O M M U N IC A IO N S

Defect Generation Statistics in Thin Gate Oxides

We analyze data-retention experiments for flash memory arrays with thin tunnel oxide (t/sub ox/ = 5 nm). These samples show an additional conduction mechanism besides Fowler-Nordheim tunneling and stress-induced leakage current (SILC). The additional leakage contribution is analyzed with respect to the spatial distribution in the array and the shape of the current-voltage characteristics, and is interpreted as an anomalous SILC due to a two-trap leakage path. From the cycling dependence of the distribution tails related to one- and two-trap leakage, we provide evidence that the defect generation statistics is not Poissonian, but is instead correlated. Possible physical mechanisms responsible for correlated generation are also discussed.

Composition and Growth Kinetics of the Interfacial Layer for MOCVD HfO2 Layers on Si Substrates

To boost MOS transistor performance, thickness of the gate dielectric is continuously scaled down. This results in an increase of gate tunneling leakage current, which at some point prevents further downscaling. Desired parameters of alternative materials to are a higher dielectric constant (high-k materials), stability, and compatibility with silicon. A general observation for one of the prime candidates, is formation of an interfacial layer between the silicon and the high-k material that limits scalability because of its low k-value. Hence, a thorough study of the formation of this layer and its contribution to the equivalent oxide thickness is of utmost importance. We studied the composition and growth kinetics of the interfacial layer formed during the deposition of by metallorganic chemical vapor deposition using and tetrakis-diethylamidohafnium as precursor. We found the composition and thickness of the interfacial layer to be dependent on the deposition parameters as well as on the starting surface. The layer’s composition is hafnium silicate-like and its thickness increases as a function of deposition time and temperature. It is therefore controlled by deposition of the layer. © 2004 The Electrochemical Society. All rights reserved.

Reliability Characteristics of poly Si-gated High Quality Chemical Vapor Deposition Hafnium Oxide Gate Dielectric

In this paper, reliability characteristics of chemical vapor deposition (CVD) HfO2 gate stacks with n+-poly-Si gate electrode are investigated systematically, along with long-term lifetime projection. The area dependence and critical defect density of CVD HfO2 gate stacks have been investigated and compared to that of SiO2. Results show that in addition to the significant reduction of tunneling leakage current by a factor of 103–104, a comparable Weibull slope factor and critical defect density are obtained from a high quality CVD HfO2 mainly due to the thicker physical thickness, compare to SiO2. Considering the cumulative impact of temperature acceleration at 150°C, scaling of an effective gate oxide area of 0.1 cm2 and a maximum allowed fraction of failures of 0.01%, the maximum allowed operating voltage is projected to be ∼0.85 V for HfO2/poly-Si gate stack with equivalent oxide thickness (EOT) = 14.5 Å.

Thickness of surface thin oxide layers determined by impedance spectroscopy using silicon/oxide/electrolyte (SOE) structures

The differential capacitance of SiO2 ultra-thin layers on Si substrate is greatly sensitive to the space charge generated within the semiconductor. In the potential scan, the determination of the capacitance/voltage characteristics in MOS devices is hindered by the high value of the tunneling leakage current. In this work, the difficulty was overcome by careful measurement of the impedance diagrams using a semiconductor/oxide/electrolyte (SOE) structure, under zero current flow. Depending on the bias potential we obtained RC equivalent circuits corresponding either to the depletion layer or to the oxide dielectric film. A novel aspect of the work is that both R and C components were derived from the data processing.In a previous work the investigation was focussed on the depletion layer, and lead to values of the resistance term in the range of a few kΩ to a few MΩcm2, while the capacitance value was a few 10−2μFcm−2. These results were consistent with a theoretical treatment of the bias voltage dependence of the charge distribution near the flatband potential, and constitute a new technique for the determination of the fb potential versus a reference electrode.The present work is devoted to the electrical properties of the Si surface oxide layer. The leakage resistance term of the thermal oxide layer, a few nm thick, was found equal to several 108Ωcm2. But, the electric field within the semiconductor is not effective for the full charge of the oxide capacitance even when the polarization creates an accumulation layer. In accordance with the computed electric field within the semiconductor, the right value of the capacitance can be reached easily when the wafer is submitted to light radiation and provided the polarization of the substrate is such as to generate an inversion layer. This property leads to an accurate method for ultra-thin insulators characterization excluding tunnel leakage current.

Scaling limits of hafnium–silicate films for gate-dielectric applications

The scaling limits of hafnium–silicate (Hf–silicate) films for use as the gate dielectric material in complementary metal–oxide–semiconductor field-effect transistors are investigated. Scalability is gauged by a figure of merit taken from the analytical model for direct tunneling leakage current. Based on the compositional dependence of this figure of merit, pure HfO2 is more scalable than Hf–silicates. However, the formation of intermediate oxide layers at the Si interface can limit the scalability of HfO2 to ∼1.0 nm equivalent SiO2 thickness (EOT). The use of Si3N4 as a diffusion barrier can prevent the formation of these interfacial layers and thereby yield lower EOT. Alternatively, 20% Hf–silicate may be more scalable than pure HfO2 with interfacial oxide layers.

Thermal response of MOCVD hafnium silicate

As complementary metal oxide semiconductor (CMOS) devices continue to scale along the rapid performance and miniaturization pace of Moore’s Law, the unacceptably high direct tunneling leakage current through the thin transistor gate insulator layer is of increasing concern. To this end, gate insulator materials with significantly higher dielectric constants ( k=10–25) continue to be investigated as potential replacements for silicon dioxide, SiO 2 ( k=3.9), and silicon oxynitride. This challenge provides opportunities for integration of a physically thicker film with lower leakage current and with capacitance equivalent to <1.0 nm SiO 2. Local changes in the composition of the candidate material, uncapped metal–organic chemical vapor deposited (MOCVD) hafnium silicate, (HfO 2) x−1 (SiO 2) x , have been evaluated by several techniques, including grazing incidence X-ray diffraction (GI-XRD), time-of-flight secondary ion mass spectroscopy (ToF-SIMS) and high angle annular dark field scanning transmission electron microscopy (HAADF-STEM). Hafnium silicate gate dielectric transistor performance data comparing high- k films with post-deposition anneal (PDA) treatments of NH 3 and N 2 at various process temperatures are presented. Changes in the material microstructure associated with phase segregation and crystallization as a function of Hf silicate composition and anneal temperature have been observed and discussions of the corresponding reaction mechanisms are presented.

Comprehensive noise performance of ultrathin oxide MOSFETs at low frequencies

An analytical model and analysis of the low frequency noise performance of ultrathin oxide MOSFETs are presented. The model includes the effects of gate tunneling leakage current, low frequency noise sources, and their cross correlation coefficient between the input and the output. The correlation coefficient is not negligible in the existence of direct tunneling current through the gate oxide, and has an impact on the overall noise performance at low frequencies. Based on the partition noise theory and BSIM4 gate leakage current model with the source–drain partition, the correlation coefficient is obtained from a physical and rigorous modeling of intrinsic noise sources. The calculated results are compared with correlation noise measurements and good agreement is observed. An analytical formulation of low frequency noise performance is newly derived using the frequency-dependent noise parameters P LF, R LF, and C LF. The noise performance parameters, such as minimum noise figure, optimum source resistance and reactance, are graphically presented to accurately predict the influence of the gate leakage current on the low frequency noise performance. From quantitative results simulated with typical device parameters, it is shown that the proposed model can be used for optimum design of ultrathin oxide MOS devices and circuits at low frequencies.

Study on Nano Complementary Metal Oxide Semiconductor Gate Leakage Current

This work examines different components of the leakage current in scaled N and P-metal oxide semiconductor field-effect transistor (MOSFET) with ultra thin gate oxide. Experimental results show that the gate tunneling leakage current through the source/drain extension region (also named edge direct tunneling, EDT) is the largest component, which dominates the maximum off-state power consumption of a nano-scaled transistor. To clarify the relationship between this largest leakage component and the size of the source/drain to gate overlap region, the proposed capacitance–ratio method (C–R method) was used to precisely extract the dimensions of the source/drain to gate overlap, Lov. To reduce the gate-tunneling leakage at the source/drain edge, a modified gate dielectric structure is proposed and verified in this work.