Study on Nano Complementary Metal Oxide Semiconductor Gate Leakage Current

Abstract

This work examines different components of the leakage current in scaled N and P-metal oxide semiconductor field-effect transistor (MOSFET) with ultra thin gate oxide. Experimental results show that the gate tunneling leakage current through the source/drain extension region (also named edge direct tunneling, EDT) is the largest component, which dominates the maximum off-state power consumption of a nano-scaled transistor. To clarify the relationship between this largest leakage component and the size of the source/drain to gate overlap region, the proposed capacitance–ratio method (C–R method) was used to precisely extract the dimensions of the source/drain to gate overlap, Lov. To reduce the gate-tunneling leakage at the source/drain edge, a modified gate dielectric structure is proposed and verified in this work.