On Composite Leakage Current Maximization

Abstract

Sub-threshold, gate and reverse biased junction band-to-band tunneling leakage currents depend on the logic inputs of a CMOS circuit. In this paper, we consider all leakage currents together and generate pattern with the objective of maximizing the overall leakage current to avoid any optimism in leakage current estimation. The computation involves Boolean reasoning on a pre-characterized set of interconnected gates. This problem is known to be computationally intractable. We propose a heuristic with reduced complexity by looking for a lower and an upper bound instead. The bounds tighten progressively with computation and converge asymptotically on a provably exact solution. By appropriately setting the objective function, the same algorithm may also be applied to find the pattern that minimizes the leakage power in the system idle state, which is considered to be ~50% of the total power consumed in the current technology generations.