Tunnel Field-effect Transistor Structure Research Articles

Investigation of Reliability Issues in a hybrid Extended Dual Source Double Gate Tunnel FET

This paper presents the design and analysis of an enhanced tunnel field-effect transistor (TFET) structure. The proposed structure comprises a dual source and a double gate, aiming to enhance the DC characteristics of the TFET. The dual source concept is used in the structure with two homogeneous gates, which play a major role in boosting the tunneling parameters. It also examines the affectability of source dimensions and drain doping on the performance of the proposed device. Furthermore, we have compared our proposed structure with the single source device. The proposed device after optimization exhibits an extraordinary I ON/I OFF ratio of 2.33 × 1013, with an I OFF of 6.25 × 10−19A/µm, and decent I on of 1.46 × 10−5A/µm along with a subthreshold swing (SS) of 43 mV/dec. The device characteristics have been analyzed in the presence of interface traps. The electrical parameters have been quantified against various types and concentrations of traps. The performance of the proposed device has been compared with the existing TFET structures.

Endurance Behavior of Z-Shaped Charge Plasma Tunnel FET for Biosensing Application

The tunneling field effect transistor (TFET) is a viable candidate for designing a highly sensitive biosensor. In this work, a doping-less Z-shaped dielectrically modulated charge plasma TFET (CPTFET) structure with misaligned cavity region on channel and source has been proposed for label-free biosensing applications. To design the device, charge plasma technique has been employed, where appropriate metal workfunction is used over intrinsic silicon to create n[Formula: see text] drain and p[Formula: see text]source regions. The charge plasma approach reduces thermal budget, random dopant fluctuation (RDF) and steps required for fabrication. The Z-shaped CPTFET includes the advantage of abrupt profile of doping at source-channel (tunneling) junction. Because cavities are created in source and gate oxide region, the abrupt doping profile suppresses ambipolar behavior and improves sensitivity. The performance of the proposed device for both charged and neutral biomolecules in terms of electric field, band energy, transfer characteristics, [Formula: see text] ratio and subthreshold swing (SS) has been examined. The response of other parameters like cavity thickness and cavity length on ON current has been analyzed using the Silvaco ATLAS device simulator.

Implementation and performance analysis of QPSK system using pocket double gate asymmetric JLTFET for satellite communications

This work is intended to design a quadrature phase shift keying (QPSK) system starting from the device design, characterization and optimization which is then followed by the circuit level implementation and finally the system level configuration. Tunnel Field Effect Transistor (TFET) technology came into existence because of the inability of CMOS (Complementary Metal Oxide Semiconductor) to produce reduced leakage current (Ioff) in the subthreshold regime. With the effects of scaling and requirement of high doping concentrations, TFET is not capable to produce stable reduction in Ioff due to the variation in ON and OFF current. To improve the switching ratio of the current and to obtain good subthreshold swing (SS) by overcoming the limitations of junction TFET, a new device design is proposed for the first time in this work. A pocket double gate asymmetric Junction less TFET (poc-DG-AJLTFET) structure has been proposed in which uniform doping is used to eliminate the junctions and a pocket of length 2 nm made of Silicon–Germanium (SiGe) material has been introduced to improve the designed structure performance in the weak inversion region and increase the drive current (ION). The work function has been tuned to produce the best results for poc-DG-AJLTFET and with our proposed poc-DG-AJLTFET, effects of interface traps are eliminated as against conventional JLTFET structures. The notion that low-threshold voltage device yields high IOFF has been proved wrong with our poc-DG-AJLTFET design, as it produced low threshold voltage with lower IOFF which reduced the power dissipation. Numerical results show that drain induced barrier lowering (DIBL) of 2.75 mV/V is achieved which could be less than 35 times required for short channel effects to be minimum. In terms of gate to drain capacitance (Cgd), it is found that ~ 103 reduction which greatly improves device inertia to internal electrical interference. Also, improvement in transconductance is achieved by 104 times, 103 times improvement in ION/IOFF ratio, and 400 times higher unity gain cutoff-frequency (ft) which would be required by all communication systems. The Verilog models of the designed device are used to construct the leaf cells of quadrature phase shift keying (QPSK) system and the implemented QPSK system is taken as a key evaluator in the performance evaluation in terms of propagation delay and power consumption of poc-DG-AJLTFET in modern satellite communication systems.

Qualitative Analysis of DG-TFET Structures with Gate Material Engineering

The paper largely focuses on enhancing device parameters of a Double Gate Tunnel Field Effect Transistor structure such as ON current, OFF Current,transconductance and ratio of ON current to OFF current (ION / IOFF) using hetero dielectric gate material. The paper presents three state of art of dual gate TFET i.e., Conventional Double Gate TFET (CDGTFET), horizontally placed Dual Material Double Gate TFET (HDMDGTFET), vertically placed Dual Material Double Gate TFET (VDMDGTFET). The dual material dielectric combinations used in the structures are (SiO2-TiO2), (HfO2-TiO2) and (SiO2-SiC). The Structures are being modeled using Silvaco Atlas tool. Simulations of these structures are carried out and various electrical parameters have been obtained. The results obtained from simulation of these structures are being presented and discussed in this paper. Comparison of the three structures is carried out and resulted in the reduction of ON Current and OFF Current is observed.

TCAD analysis of tunnel field effect transistor using Ge material for low power application

Low power is important parameter for any semiconductor devices. In transistors the current flow between source to drain through channel region is dependent upon the materials of source, drain and channel. This paper presents a detailed study of the role of Technology Computer-Aided Design (TCAD) simulations of tunnel-field-effect-transistor (TFET) for low power applications with Germanium (Ge) material. Ge has band gap 0.66 V and the most suitable candidate to improve TFET performance. The need and importance of TCAD tool in semiconductor technology development is explained in details in this manuscript. It also elaborates the TCAD techniques for designing a device, parameter extraction and different models that are used to design different TFET structure. TCAD based digital logic design, design for manufacturing, memory designing and reliability study have been also discussed in this paper.

Insights into temperature influence on analog/RF and linearity performance of a Si/Ge heterojunction asymmetric double gate dopingless TFET

The charge-plasma based dopingless (DL) tunnel field effect transistor (TFET) is considered as an emerging TFET structure resulting from its immunity against random dopant fluctuations and not requiring high thermal budgets and expensive annealing methods for fabrication. But, temperature sensitivity is a major concern to predict the reliability of a device as the bandgap of semiconductor material changes under the influence of temperature variations when used in a system. Therefore, in this manuscript, the effect of variations in temperature (200–500 K) are investigated on the analog/RF and linearity characteristics of a Si/Ge hetero-junction (HJ) asymmetric double gate (ADG) DLTFET and abbreviated as HJ-ADG-DLTFET in the entire manuscript. In this context, Silvaco ATLAS simulator is used to evaluate DC and Analog/RF performance parameters such as $$I_{D}-V_{G}$$ characteristics, transconductance ( $$g_{m}$$ ), cut off frequency ( $$f_{T}$$ ) and transconductance generation factor (TGF) considering effect of temperature variations. Furthermore, linearity parameters such as second- and third-order voltage intercept point ( $$\mathrm{VIP}_{2}, \mathrm{VIP}_{3}$$ ), 1-dB compression point, third-order input-interception point ( $$\mathrm{IIP}_{3}$$ ) and intermodulation distortion $$(\mathrm{IMD}_{3})$$ are also evaluated considering temperature variations as these FoM are significant for linear and analog/RF applications.

Numerical simulations of a novel CH3NH3PbI3 based double-gate dopingless tunnel FET

Tunnel field effect transistors (TFETs) are generating considerable interest in switching applications due to their steep-subthreshold slope achieved by the quantum mechanical tunneling as a switching mechanism. However, all TFET structures currently in vogue based on Si, Ge or III–V materials have not been able to satisfy the other stringent requirements like higher on current (I ON) and low cost of fabrication. We, in this paper, report a cost-effective, organic–inorganic hybrid perovskite CH3NH3PbI3 material-based DG–DL TFET (labeled as MAPbI3–DG–DL TFET hereinafter) which has been shown to adapt to the advantages of the double gate (DG) and doping less (DL) technique for better electrostatic control and low thermal budget respectively. In simulations conducted using Silvaco Atlas tool at room temperature and supply voltage of 1 V on the proposed device structure, we have been able to achieve subthreshold swing of 27.33 mV decade−1, cut-off frequency of 0.268 THz and switching ratio of 1.85 × 1011. Detailed explanations of the results provided in the paper tend to establish that MAPbI3–DG–DL TFET could be a suitable candidate for low-power and high-speed logic applications.

Effect of dielectric pocket for controlling ambipolar conduction in TFET and analysis of noise and temperature sensitivity

An n+ pocket-doped silicon on insulator (SOI) tunnel field effect transistor (TFET) along with a dielectric pocket (DP) at channel drain junction has been proposed and investigated in this article. The merged impact of both lateral and vertical tunneling due to n+ pocket in the gate–source overlap region enhances the ON current and provides steeper subthreshold swing (SS). The dielectric pocket at channel drain junction depletes the drain region at channel drain interface. Consequently, the minimum tunneling width at channel drain interface is enhanced to offer significant suppression of ambipolar conduction in a TFET. The proposed TFET structure offers a high ON/OFF current ratio of 1.57 × 1010 and considerably low SS of 8 mV/dec along with reduced ambipolar conduction up to a larger negative bias region. The impact of parametric variation of the proposed structure is studied and optimized accordingly. Noise characteristics of the proposed SOI TFET are investigated to realize the reliability issues of the device. Besides, the impact of elevated temperature on transfer characteristic and various RF parameters including transconductance (gm), total gate capacitance (Cgg), gate to drain capacitance (Cgd), cutoff frequency (ft), gain bandwidth product (GBP) and intrinsic delay (τ), respectively, have been investigated. The device performance has been upgraded by the rise in cutoff frequency and drop in intrinsic delay at high temperature.

Performance Analysis of Group IV Material Based Tunnel Field Effect Transistor: Effect of Drain Splitting and Introducing Ge-Strip at Source- Channel Junction

The performance effect of splitting and abrupt doping in the drain region, use of a Ge strip at source-channel junction in group IV material based (Ge1 − xSnx/ Si1 − y − zGeySnz) Tunnel Field Effect Transistor (TFET) is investigated in the present manuscript. The variation of certain device parameters, such as mole fraction, different gate dielectrics, gate dielectric thickness and drain doping concentrations are applied to analyze the performance of proposed group IV material based TFET in terms of current-voltage (I-V) characteristics, potential profile and ION/IOFF ratio using device simulator SILVACO TCAD. The simulation results obtained for the proposed TFET structure are compared with the other TFET structures available in the literature, which shows better results as ION/IOFF ratio was received of the order of 1012 in comparison to conventional group IV material based TFET and subthreshold swing of 25.03 mV/decade, which makes the proposed structure promising for high speed switching action with low power CMOS compatibility.

Evanescent mode based compact modelling of a dual‐metal double‐gate tunnel field‐effect transistor

In this study, channel potential for silicon-based doped dual-metal double-gate tunnel field-effect transistor structure is analytically solved using the evanescent-mode approach in the sub-threshold region. This method generally describes short channel effects in the entire channel region of the device structure and predicts different characteristic length λ which depends on tunnel current and does not depend along a transverse direction within the channel. The model is valid for the whole device structure rather than just semiconductor/insulator interfaces. The impact of variation of bias condition on channel potential is also investigated in the sub-threshold region. Finally, drain current is evaluated using Kane's and Kleysh's model and validated with a calibrated simulation, which has been carried out using 2D TCAD Sentaurus simulator.

A novel source material engineered double gate tunnel field effect transistor for radio frequency integrated circuit applications

Tunnel field effect transistors (TFETs) have proved their potential for many possible electronic circuit applications. However, with the variety of TFET structures being worked upon it has been an unresolved challenge to optimize them for the applications to which they are best suited. In this paper we present a detailed comparative analysis of the linearity distortion and the radiofrequency (RF) performance parameters of a proposed heterojunction Mg2Si source double gate TFET (HMSDG-TFET) and a conventional homojunction Si source DG-TFET (SSDG-TFET). A source material engineering scheme is utilized to implement a staggered type 2 heterojunction at the source–channel junction by replacing the source material with Mg2Si (a low band gap material) to enhance the ON current (2.5 × 10–4 A µm−1), reduce the threshold voltage (0.26 V) and achieve a steeper subthreshold swing (10.05 mV decade−1). For linearity and distortion analysis, the figure of merit (FOM)-like higher-order transconductances, second- and third-order voltage intercepts, third-order intercept point, third-order intermodulation distortion, zero crossover point, 1 dB compression point, second-order harmonic distortion, third order harmonic distortion and total harmonic distortion have been examined. To portray the possible application of devices under consideration for RF integrated circuit applications, both structures are investigated for RF FOMs such as power gains, cutoff frequency (fT), maximum oscillation frequency (F max) and admittance parameters. Investigations carried out using a Silvaco ATLAS device simulator tool revealed that with fT approximately three orders higher (0.49 THz) and F max approximately two orders higher (0.9 THz) than that of a SSDG-TFET, the HMSDG-TFET is an appropriate candidate for use in high-frequency, high-linearity, low-distortion and low-power analog/RF applications.

A simulation study of the influence of a high-k insulator and source stack on the performance of a double-gate tunnel FET

The influence of incorporating HfO2 as a dielectric at the drain side and a silicon stack at the source side on the electrical performance of a double-gate tunnel field-effect transistor (TFET) is investigated by comparing a conventional TFET structure with four other structures in which the gate dielectric material is either homogeneous or heterogeneous while the insulator on the drain side is either SiO2 or HfO2. Moreover, a structure with a silicon source stack is proposed and the figures of merit of the resulting device are compared with other counterparts. The results of the simulations reveal that the presence of an HfO2 insulator on the drain side reduces the ambipolar conduction while the heterogeneous gate dielectric enhances the drive current and transconductance. However, the use of HfO2 slightly deteriorates the source–gate and drain–gate capacitances in comparison with the conventional TFET. Furthermore, the incorporation of a silicon source stack along with a heterogeneous gate dielectric and HfO2 insulator on the drain side leads to a higher ION/IOFF ratio, lower subthreshold slope (S), and lower ambipolar conduction in the studied TFET with channel length of 50 nm.

Controlling the ambipolar current in ultrathin SOI tunnel FETs using the back-bias effect

A two-dimensional (2-D) technology computer-aided design (TCAD)-based simulation study of the back bias in the ultrathin silicon-on-insulator (SOI) tunnel field-effect transistor (TFET) is presented. The transfer characteristics of a conventional TFET called the back-bias TFET (BB-TFET) depend on the back bias and the oxide thickness below the TFET epitaxial layer. The back bias affects the electric field at the source/channel and drain/channel junctions, hence both the ON-state current ($$I_{\mathrm{ON}}$$) and the ambipolar current ($$I_{\mathrm{AMB}}$$) reduce with a negative back-bias voltage. This reduction in $$I_{\mathrm{ON}}$$ is not desirable in a TFET, hence a modified TFET structure called the back-bias underdrain TFET (BBUD-TFET) is proposed. In the BBUD-TFET, the back bias is applied on a p-Si pocket placed under the drain region, which is isolated using an ultrathin oxide. The back bias in the proposed BBUD-TFET mainly affects the electric field at the drain/channel interface, having a negligible impact on the source/channel interface. The BBUD-TFET structure is analyzed with $${\mathrm{SiO}}_2$$ or $${\mathrm{HfO}}_2$$ as the gate oxide. In the BBUD-TFET with $${\mathrm{HfO}}_2$$ as the gate oxide, the back bias completely suppresses the ambipolar current without reducing $$I_{\mathrm{ON}}$$. Furthermore, the oxide thickness and back-bias voltage are optimized for the BBUD-TFET structure. In this study, 2-D TCAD simulations are carried out to investigate and analyze the performance of the BB-TFET and BBUD-TFET.

Analysis of kink reduction and reliability issues in low‐voltage DTD‐based SOI TFET

This work proposes a silicon-on-insulator (SOI) tunnel field-effect transistor (TFET) with highly doped p ++ -type L-shaped trench, which creates two dual tunnel diodes (DTDs) and compares the results with conventional SOI (C-SOI) TFET structure. Kink effect is analysed in SOI TFET, and for eliminating kink effect, a method has been proposed. The tunnel current of the DTD eliminates the accumulation of holes and mitigates the kink effect. The impact of temperature variation on kink effect has been studied. In the case of C-SOI device, kink effect postpones with the rise in temperature and the DTD-SOI device provides improved performance even at high temperature with no kink in the current-voltage characteristics. Moreover, the reliability issues of DTD-SOI device have been examined by considering various noise components in the presence of interface traps.

Dual‐channel trench‐gate tunnel FET for improved ON‐current and subthreshold swing

In this Letter, a dual-channel trench-gate tunnel field-effect transistor (DCTG-TFET) is proposed and investigated. The gate of DCTG-TFET is placed vertically in a trench to create two channels which carry drain current in parallel. The proposed device dimensions are optimised to reduce channel resistance and tunnelling width for an appreciable increase in the ON-state current (). The performance of DCTG-TFET is analysed using two-dimensional simulations in the device simulator. The proposed DCTG-TFET provides one order of magnitude improvement in / current ratio and 17 times reduction in subthreshold swing as compared to recently reported two-source-region tunnel field-effect transistor structure.

Analytical Modeling and Simulation-Based Optimization of Broken Gate TFET Structure for Low Power Applications

In this paper, we have reported a renovated silicon-based tunnel field-effect transistor (TFET) structure with a channel length of 21 nm. The proposed structure has been optimized and analytically modeled. The broken gate TFET (BG-TFET) shows very low ambipolar current, good subthreshold swing (SS) and ON-currents comparable to the contemporary structures of similar dimensions. The surface potential and the electric field inside the device are modeled by solving the 2-D Poisson’s equation. The drain current is also modeled based on Kane’s generation rate. The results obtained from the analysis are validated against Synopsys Sentaurus TCAD nonlocal tunneling model-based simulations.

Reduction of the kink effect in a SELBOX tunnel FET and its RF/analog performance

The kink effect in a fully depleted silicon-on-insulator (SOI) tunnel field-effect transistor (TFET) is studied and compared with the results for a SOI metal–oxide–semiconductor field-effect transistor (MOSFET) using a model that is calibrated against experimental results available in literature. A technique for eliminating the kink effect is proposed. The structure with a small gap in the buried oxide, known as the selective buried oxide (SELBOX) structure, is capable of reducing the kink effect. The impact of the kink effect on the device performance for different gap positions, thicknesses, and buried oxide thicknesses is examined. A better current–voltage characteristic is obtained for a position of the gap near the source. The effect of varying the temperature and the presence of a uniform trap charge on the kink effect for the SOI TFET, SOI MOSFET, and SELBOX structures is also studied. Various electrical parameters such as the subthreshold swing and ION/IOFF ratio are investigated for the TFET in the presence and absence of uniform trap charge. Although the SELBOX structure can minimize the kink effect, it is still present for such devices with narrow and wider gaps. Therefore, the gap thickness is optimized based on technology computer-aided design (TCAD) simulations. Furthermore, radio frequency (RF)/analog performance parameters such as the transconductance (gm), cutoff frequency (ft), transconductance generation factor (TGF = gm/ID), transconductance frequency product, gain transconductance frequency product, and 1-dB compression point are investigated using TCAD simulations and compared between the SELBOX MOSFET and SELBOX TFET devices.

A Charge Plasma-Based Monolayer Transition Metal Dichalcogenide Tunnel FET

In this paper, a charge plasma-based monolayer transition metal dichalcogenide (TMD) tunneling field-effect transistor (TFET) is investigated by solving self-consistent 3-D Poisson and Schrodinger equations in nonequilibrium Green’s function (NEGF) framework. We propose a work function engineered charge plasma-based dual-metal source TFET (DMS TFET) structure for an optimum performance of the device. The proposed TFET structure demonstrates superior performance than the conventional charge plasma TFETs in terms of ${I}_{{\scriptscriptstyle {\text {ON}}}}$ , ${I}_{{\scriptscriptstyle {\text {ON}}}}/{I}_{{\scriptscriptstyle {\text {OFF}}}}$ ratio, and subthreshold slope (SS). It provides ${I}_{{\scriptscriptstyle {\text {ON}}}}$ of $222~\mu \text{A}/\mu \text{m}$ , ${I}_{{\scriptscriptstyle {\text {ON}}}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of $2.22\times 10^{{5}}$ , a minimum SS of 42.41 mV/decade, and an average SS of 54.15 mV/decade for three-decade increase in drain current ( ${I}_{\text {DS}}$ ). The performance of the device is observed at different channel lengths. Based on this analysis, a device design guideline for sub-10-nm channel length TFETs is presented in the paper. Finally, the circuit level metrics of the proposed structure are estimated by calculating delay and energy-delay product of a 45-stage inverter chain.

High On-Current Ge-Channel Heterojunction Tunnel Field-Effect Transistor Using Direct Band-to-Band Tunneling.

The main challenge for tunnel field-effect transistors (TFETs) is achieving high on-current (Ion) and low subthreshold swing (SS) with reasonable ambipolar characteristics. In order to address these challenges, Ge-channel heterostructure TFET with Si source and drain region is proposed, and its electrical characteristics are compared to other TFET structures. From two-dimensional (2-D) device simulation results, it is confirmed that the Si/Ge heterostructure source junction improves Ion and SS characteristics by using the direct band-to-band tunneling current. Furthermore, the proposed structure shows suppressed ambipolar behavior since the Ge/Si heterostructure is used at the drain junction.

Influence of Doping and Splitting of Source in a Group IV Material Based Tunnel Field Effect Transistor

In this work, the effect of abrupt source doping in a tunnel field effect transistor (TFET) using SiGe as the source and drain material is investigated for future low-voltage and high-power applications. The effect of critical device factors, such as dielectric material and gate oxide thickness and dependency on the mole fraction, are examined. The results of the proposed SiGe-Si-SiGe TFET structure are compared with existing data of Si TFET and SiGe-Si-Si TFET with and without abrupt doping. The proposed structure shows better ION/IOFF ratio of the order of 1011 and a sub-threshold swing of 18.18 mV/decade, which ensures fast switching applications of the device.