Effect of dielectric pocket for controlling ambipolar conduction in TFET and analysis of noise and temperature sensitivity

Abstract

An n+ pocket-doped silicon on insulator (SOI) tunnel field effect transistor (TFET) along with a dielectric pocket (DP) at channel drain junction has been proposed and investigated in this article. The merged impact of both lateral and vertical tunneling due to n+ pocket in the gate–source overlap region enhances the ON current and provides steeper subthreshold swing (SS). The dielectric pocket at channel drain junction depletes the drain region at channel drain interface. Consequently, the minimum tunneling width at channel drain interface is enhanced to offer significant suppression of ambipolar conduction in a TFET. The proposed TFET structure offers a high ON/OFF current ratio of 1.57 × 1010 and considerably low SS of 8 mV/dec along with reduced ambipolar conduction up to a larger negative bias region. The impact of parametric variation of the proposed structure is studied and optimized accordingly. Noise characteristics of the proposed SOI TFET are investigated to realize the reliability issues of the device. Besides, the impact of elevated temperature on transfer characteristic and various RF parameters including transconductance (gm), total gate capacitance (Cgg), gate to drain capacitance (Cgd), cutoff frequency (ft), gain bandwidth product (GBP) and intrinsic delay (τ), respectively, have been investigated. The device performance has been upgraded by the rise in cutoff frequency and drop in intrinsic delay at high temperature.