Emerging Nanoelectronic Devices

Abstract

The most striking feature of the semiconductor industry is the scaling of MOSFETs, due to which it is getting cheaper and also consuming less power. But as the MOS transistors are entering the decananometer regime, it is becoming very difficult to achieve high doping density gradients required for pn junctions. This is because of the laws of diffusion and the statistical nature of the distribution of the doping atoms in the semiconductor. Thus, novel nanoelectronic devices are needed that could enable aggressive scaling. Junctionless transistors (JLTs) are those transistors that are devoid of junctions. They are based on the concept of gate work function engineering or charge plasma concept. The idea behind the junctionless concept is the formation of a semiconductor layer that is thin and narrow enough to allow depletion of carriers when the device is turned off. A highly doped semiconductor is also required for satisfactory ON-state current. The work function of the gate material plays a very important role in determining the characteristics of the channel under the gate. However, JLTs are plagued by high OFF-state leakage current attributed to the band-to-band tunneling at the channel–drain interface. This leakage current is often referred to as gate-induced drain leakage (GIDL). The problem of GIDL is a common problem that exists in both these nanoscale junctionless transistors (JLT) and dopingless transistors (DLT). As the gate lengths are fast approaching sub-10 nm scale the problem of GIDL is a serious issue. All type of junctionless devices – JLT, JAMFET, and DLT – suffer from this problem. In this chapter, we have discussed proposed techniques to counter this effect of GIDL in JLTs. The charge plasma concept can also be used to form various p+-i-n, p+-n+-p-n+ architectures for tunnel field effect transistors (TFETs), which also rely on the concept of band-to-band tunneling, though, at the source-channel junction. As mentioned earlier, the gate material work function has a very dominant effect on the channel properties; thus, different gate materials could be used for formation of regions having different characteristics. Thus this junctionless concept could be used to form p-i-n regions for TFETs. The junctionless TFET can be a very good alternative to continue the scaling trend in TFET. The TFET device has also been realized on a dopingless structure. The concept of a DLT made possible with electrostatic doping has been extended to TFET structures. The use of electrodes to get the desired doping concentrations has been proposed successfully. The aim of this chapter is to further explore and improve these device architectures and provide solutions for issues such as low ON current and ambipolar conductivity in these junctionless TFET structures.