Analytical Model and Simulation Based Analysis of a Doped Si DG TFET Exhibiting Lower Subthreshold Slope

Abstract

A doped double gate uni-junction silicon-based novel Tunnel Field Effect Transistor (TFET) structure is proposed that exhibits lower subthreshold slope (10 mV/decade) and better ON to OFF current ratio (I on /I off is in order of 107 at low supply voltage) compared to conventional double gate TFET structure. A simulation-based analysis of the proposed structure has been carried out with the help of 2D TCAD Sentaurus device simulator at different channel length values. A mathematical model is also developed to verify the result with simulation. Our proposed TFET structure is composed of one common p region which acts as both source and channel. Therefore the configuration is basically a p-n double gate TFET having a n+ pocket close to source side and another n+ pocket close to drain side. These pockets are created separately by using work function engineering technique on metal gate having different lengths and thicknesses and also by using high k and low k dielectric as oxide. The source side n+ pocket enhances tunneling probability thus increasing I on and I off is controlled by another n+ pocket near drain side. Significantly lower subthreshold slope as observed from calibrated simulation of our proposed configuration makes this device more suitable for digital logic application.