Abstract
In this Letter, a dual-channel trench-gate tunnel field-effect transistor (DCTG-TFET) is proposed and investigated. The gate of DCTG-TFET is placed vertically in a trench to create two channels which carry drain current in parallel. The proposed device dimensions are optimised to reduce channel resistance and tunnelling width for an appreciable increase in the ON-state current (). The performance of DCTG-TFET is analysed using two-dimensional simulations in the device simulator. The proposed DCTG-TFET provides one order of magnitude improvement in / current ratio and 17 times reduction in subthreshold swing as compared to recently reported two-source-region tunnel field-effect transistor structure.
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