Gate Tunneling Research Articles

Microwave quantum optics as a direct probe of the Overhauser field in a quantum dot circuit quantum electrodynamics device

We show theoretically that a quantum-dot circuit quantum electrodynamics (CQED) device can be used as a probe of the Overhauser field in quantum dots. By coupling a transmission line to the interdot tunneling gate, an electromagnetically-induced-transparency (EIT) scheme can be established, whose Fano-type interference leads to a sharp curvature in the reflection spectrum around resonance. This sharp feature persists even in the presence of the fluctuating spin bath, rendering a high-resolution method to extract the bath's statistical information. For strong nuclear spin fields, the reflection spectrum exhibits an Autler-Townes splitting, where the peak locations indicate the strengths of the Overhauser field gradient (OFG).

Dual Metal Gate Dielectric Engineered Dopant Segregated Schottky Barrier MOSFET With Reduction in Ambipolar Current

In this paper, to solve the problem of higher ambipolar leakage current (Iambipolar) of Dielectric Engineered (DE) Dopant Segregated (DG) Schottky Barrier (SB) MOSFET (DE DS SBMOS), we have incorporated dual metal gate (DMG) in place of single metal gate for the DE DS SBMOS. The proposed device is named as DMG DE DS SBMOS. In a proposed device, the gate is consisting of dual metal having different work functions. Therefore, the gate is divided in two parts named as auxiliary gate (AG) and tunneling gate (TG). AG and TG employed near the source and drain (S/D) ends, respectively. AG is mainly used to control the on-state performance and TG for the off-state performance by modulating the SB height and width at S/D end, respectively. Simulation results show that Iambipolar of the device has been successfully suppressed by choosing appropriate work functions for AG and TG without affecting the on-state current (Ion) of the device. The proposed device combines the advantage of dual metal gate and dielectric engineering to achieve improvement in the overall performance of the device. The proposed device exhibits high Ion, low Iambipolar and low subthreshold swing (SS). The simulations study verifies the use of the proposed device for low power applications.

Sensitivity Analysis on Dielectric Modulated Ge-Source DMDG TFET Based Label-Free Biosensor

This work compares the performance of dielectric modulated (DM) based Ge-source dual material double gate (DMDG) Tunnel Field Effect Transistor (TFET) and conventional (C)-DMDG-TFET as label free biosensor through Technology Computer Aided Design (TCAD) simulator. Here, cavity is introduced both at source and drain sides of the fixed HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> dielectric to increase the capture area of biosensors. Sensitivity (S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sub> ) is extracted for both neutral and charged (positive/negative) biomolecules considering cavity is fully filled with different dielectric materials (k). We have reported the sensitivity with the variation in height of nanogap cavity (h <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bio</sub> ) for neutral biomolecules in the cavity. The sensitivity of Ge-source DMDG-TFET is found higher than C-DMDG-TFET due to more conduction at the tunnel junction. Also, the subthreshold swing (SS), transfer characteristics, and I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ratio of these biosensors are reported for different k and h <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bio</sub> considering neutral/charged biomolecules. The sensitivity of partially filled nanogaps with biomolecules like decreasing, increasing, concave, and convex step profiles are reported for both the biosensors. The dynamic range (DR) of both the biosensors are extracted in presence of positive and negative charged biomolecules. The response time of Ge-source DMDG-TFET is reported at different k. A comparative study of proposed biosensor with other reported work is discussed. Finally, the sensitivity is extracted for DMDG-TFET considering other source material like GaAs, InAs, Si-Ge hetero stacked (HS), GaAs-InAs HS.

Performance Analysis on Effect of Variation in Oxide Material of Double Gate Tunnel Field Effect Transistor

In this paper structure of Double Gate Tunnel Field Effect Transistor work to increase the efficiency of the device performance of Tunnel Field Effect Transistors making it one of the potential candidates for small scale devices. The essential point of this research work is to consider the performance analysis of the structure. This work is accomplished with the assistance of tool Cogenda TCAD version 1.9.2. The designing of the device, simulation and correlation of results have been gotten on this tool. The section gives the stream of Research Methodology and clarifies the footsteps for Design and Simulation of Double Gate Tunnel Field Effect Transistor.

Band gap and gate metal engineering of novel hetero-material InAs/GaAs-based JLTFET for improved wireless applications

This paper investigates the reliability of a dual metal gate-hetero-material junctionless tunnel FET (DMG-HJLTFET), by using a novel combination of III–V compound semiconducting materials, $$\mathrm{InAs}$$ (lower bandgap) in the source region and $$\mathrm{GaAs}$$ (higher bandgap) in the channel and drain regions. We applied bandgap engineering and dual material gate engineering to improve the linearity metrics and distortion parameters by optimizing an appropriate lower work function tunnel gate toward the source and higher work function supplementary gate toward the drain and compared all the results with SMG (single metal gate)-HJLTFET and Si-JLTFET. The DMG-HJLTFET showed marked improvements in terms of ION, ION/IOFF, SS, $${g}_{\mathrm{m}}$$ , $${g}_{\mathrm{m}3}$$ , VIP2, VIP3, and 1-dB compression point. The input power, IIP3 of DMG-HJLTFET, is 158% greater than SMG-HJLTFET and is 154.7% greater than Si-JLTFET. The distortion power, IMD3 of DMG-HJLTFET, is 171.8% and 20.5% lower than SMG-HJLTFET and Si-JLTFET, respectively, thereby making it suitable for low-power distortion-free wireless communication systems.

Drain current characterization of dielectric modulated split gate TFET for bio-sensing application

This paper presents an analytical surface potential and drain current model of split gate (SG) Tunnel Field Effect Transistor (TFET) for label free detection of biomolecules e.g. protein, biotine, DNA, etc., utilizing the concept of underlap and dielectric modulation approach. A portion of the device channel is left open in between the splitted gates with a thin layer of silicon dioxide as adhesive layer. This open cavity acts as the binding site for the biomolecules to be detected which alters the effective capacitance of the region and hence modulates the device characteristic trend. The device electrostatics are developed by solving two dimensional Poisson’s equation and Young’s parabolic approximation and consequent drain current is then formulated applying Kane’s model. To assess the sensing ability of the device, both neutral and charged biomolecules with different dielectric values are immobilized within the cavity and the impact of variation in dielectric constant, charge density and height of biomolecules on device characteristics is analyzed. In addition to this, drain current sensitivity of the device is also investigated by varying the permittivity, charge density (both positive and negative) and height of the bio-species. All the analytical results are evaluated with corresponding Sentaurus TCAD simulated data to corroborate the accuracy of the derived model.

Investigation of tri-gate hetero-junction stacked dielectric transistor for improved ON-current

Three different work functions are taken in this paper for investigating a hetero-junction tri gate tunnel FET and it is simulated using TCAD. The proposed device employs hetero-junction structure that exhibits lesser band-gap between source and intrinsic region, which leads to the improvement in On-current. Three lengths (L1, L2 and L3) are taken and the performance of the device is analyzed by considering the depletion regions of the source, channel and drain. From the simulation, parameters like drain current, surface potential, electrical field in vertical and lateral directions are obtained. Four regions are allocated in this device and are examined with different hetero-structures; materials and the model prophesy the electrostatic potential accurately. Improvisation in ON-current (10-5A) is also achieved when comparing to the performance analysis carried out using Triple Material Tri-gate TFET without a stack structure. The accuracy and characteristics of the device are evaluated using TCAD simulation.

Novel center potential based analytical sub-threshold model for dual metal broken gate TFET

PurposeThe purpose of this paper is to present an improved model based on center potential instead of surface potential which is physically more relevant and accurate. Also, additional analytic insights have been provided to make the model independent and robust so that it can be extended to a full range compact model.Design/methodology/approachThe design methodology used is center potential based analytical modeling using Psuedo-2D Poisson equation, with ingeniously developed boundary conditions, which help achieve reasonably accurate results. Also, the depletion width calculation has been suitably remodeled, to account for proper physical insights and accuracy.FindingsThe proposed model has considerable accuracy and is able to correctly predict most of the physical phenomena occurring inside the broken gate Tunnel FET structure. Also, a good match has been observed between the modeled data and the simulation results. Ion/Iambipolar ratio of 10^(−8) has been achieved which is quintessential for low power SOCs.Originality/valueThe modeling approach used is different from the previously used techniques and uses indigenous boundary conditions. Also, the current model developed has been significantly altered, using very simple but intuitive technique instead of complex mathematical approach.

Investigation of Ambipolar Conduction and RF Stability Performance in Novel Germanium Source Dual Halo Dual Dielectric Triple Material Surrounding Gate TFET

In this study, we present an ambipolar conduction and RF stability performance for a Germanium Source Dual Halo Dual Dielectric Triple Material Surrounding Gate Tunnel FET (Ge(SRC)-DH-DD-TM-SG-TFET). The energy band diagram of the device will be derived using the Stern Stability Factor. The minimum tunneling length is expressed using low-k Silicon dioxide (SiO2) and high-k Hafnium oxide (HfO2) as dual dielectric material. Then the band to band tunneling (BTBT) rate tunneling generation rate will be derived using Kane’s model. In terms of frequency efficiency the proposed device with SiO2/HfO2 as gate dielectric is good enough to attain high cut-off frequency (fT) of 94.22 GHz is observed at drain to source voltage of VDS = 1 V. Efforts have also been made to properly assess the potential of the two halo doped regions regions. An expression for transconductance is proposed and the model is validated using 3-D Silvaco Atlas TCAD device simulator. In addition, to demonstrate the advantage of using Ge(SRC)-DH-DD-TM-SG-TFET dual dielectric halo doping in circuit applications, the transient response of the conventional TFET germanium source is compared with the low and high-k dielectric halo doping Ge(SRC) TFET.

Low-K Dielectric Pocket and Workfunction Engineering for DC and Analog/RF Performance Improvement in Dual Material Stack Gate Oxide Double Gate TFET

In this paper, we investigate the effect of low K dielectric pocket on DC and analog/RF performance in dual material stack gate oxide double gate tunnel field effect transistor. For this, we have considered an optimized dielectric pocket at the interface of the source-channel tunneling junction to reduce the barrier width. A stack gate oxide (SiO2 + HfO2) with workfunction engineering is applied to improve the capacitive coupling, decrease the ambipolar, leakage currents and increase the ON-current (ION). In addition, the entire gate has been divided into three segments, named as tunnelling gate (M1) with workfunction (ϕ1), Control gate (M2) with workfunction (ϕ2) and auxiliary gate (M3) with workfunction (ϕ3). All the possible combinations of these workfunctions were considered to maintain dual work functionality. Further, technology computer-aided design (TCAD) simulations for these possible combinations were carried out and compared with single material stack gate oxide dual gate source dielectric pocket TFET (ϕ1 = ϕ2 = ϕ3). Simulation results shows that the workfunction combination (ϕ1 = ϕ3 < ϕ2) outperforms the other three structures. Further, the performance of this device is compared with dual material control gate source dielectric pocket TFET (DMCG-SDP-TFET) with SiO2 gate oxide. The dielectric pocket at the tunneling junction and workfunction engineering on the stack gate oxide shows significant enhancement in ON state current (1.47× 10− 4A/μm), ION/IOFF (3.14× 1012), point subthreshold slope (15.7mV/decade), transconductance (1.02× 10− 3S), cut-off frequency (1.93× 1011Hz) and significant changes in other analog/RF performance parameters, making this device suitable for high frequency and low power applications.

Hard-Gap Spectroscopy in a Self-Defined MesoscopicInAs/AlNanowire Josephson Junction

Superconductor/semiconductor-nanowire hybrid structures can serve as versatile building blocks to realize Majorana circuits or superconducting qubits based on quantized levels such as Andreev qubits. For all these applications it is essential that the superconductor-semiconductor interface is as clean as possible. Furthermore, the shape and dimensions of the superconducting electrodes needs to be precisely controlled. We fabricated self-defined InAs/Al core/shell nanowire junctions by a fully in-situ approach, which meet all these criteria. Transmission electron microscopy measurements confirm the sharp and clean interface between the nanowire and the in-situ deposited Al electrodes which were formed by means of shadow evaporation. Furthermore, we report on tunnel spectroscopy, gate and magnetic field-dependent transport measurements. The achievable short junction lengths,the observed hard-gap and the magnetic field robustness make this new hybrid structure very attractive for applications which rely on a precise control of the number of sub-gap states, like Andreev qubits or topological systems.

Simulation Study of Dielectric Modulated Dual Channel Trench Gate TFET-Based Biosensor

A dielectric modulated dual channel trench gate tunnel FET (DM-DCTGTFET) based biosensor is proposed for label-free detection of biomolecules. The gate of DM-DCTGTFET is placed vertically in a trench for creating two channels on both sides of the gate. The parallel conduction of two channels enhances the current of the DM-DCTGTFET. Further, in the proposed structure, two cavities are carved in the gate-oxide on either side of gate for biomolecules immobilization. The sensitivity performance of DM-DCTGTFET is analyzed using 2D simulations in the TCAD tool (ATLAS). The proposed structure exhibits high current sensitivity (~1012) as well as exorbitant voltage sensitivity ( $5.2 {V}$ ) which are significantly higher than the recently reported TFET based biosensors. Therefore, the DM-DCTGTFET biosensor is a highly promising structure due to dual sensing capabilities for biomolecules.

Reduction of charge offset drift using plasma oxidized aluminum in SETs

Aluminum oxide ({text {AlO}}_x)-based single-electron transistors (SETs) fabricated in ultra-high vacuum (UHV) chambers using in situ plasma oxidation show excellent stabilities over more than a week, enabling applications as tunnel barriers, capacitor dielectrics or gate insulators in close proximity to qubit devices. Historically, {text {AlO}}_x-based SETs exhibit time instabilities due to charge defect rearrangements and defects in {text {AlO}}_x often dominate the loss mechanisms in superconducting quantum computation. To characterize the charge offset stability of our {text {AlO}}_x-based devices, we fabricate SETs with sub-1 e charge sensitivity and utilize charge offset drift measurements (measuring voltage shifts in the SET control curve). The charge offset drift (Delta {Q_0}) measured from the plasma oxidized {text {AlO}}_x SETs in this work is remarkably reduced (best Delta {Q_0}=0.13 , hbox {e} , pm , 0.01 , hbox {e} over approx 7.6 days and no observation of Delta {Q_0} exceeding 1, hbox {e}), compared to the results of conventionally fabricated {text {AlO}}_x tunnel barriers in previous studies (best Delta {Q_0}=0.43 , hbox {e} , pm , 0.007 , hbox {e} over approx 9 days and most Delta {Q_0}ge 1, hbox {e} within one day). We attribute this improvement primarily to using plasma oxidation, which forms the tunnel barrier with fewer two-level system (TLS) defects, and secondarily to fabricating the devices entirely within a UHV system.

Impact of trap charge and temperature on DC and Analog/RF performances of hetero structure overlapped PNPN tunnel FET

Impact of interface trap charges (ITCs) as well as temperature on the performance of a proposed dual dielectric constant spacer source/drain, overlapped double gate tunnel FET with a source pocket was investigated using two-dimensional Technology Computer-Aided Design (TCAD) device simulator. The proposed device is Si-based with Germanium as the source material, SiGe as a pocket material, and has a high-k gate dielectric. Its performance in terms of DC and analog/RF parameters vis-a-vis a conventional double gate PNPN TFET was compared. The device shows better results than the conventional one with an ON current of 1.71 × 10−3 A/µm, ON–OFF current ratio 1011, and subthreshold swing of 45 mV/decade. The study was focused on the analysis of the electric field, transfer characteristics, transconductance (gm), output conductance (gd), parasitic capacitances, gain-bandwidth product (GBP), cut off frequency (fT) for both the damaged (presence of donor/acceptor interface trap charges) and undamaged (no trap) conditions. The study revealed that the proposed structure is more immune to the interfacial trap charges as compared to the conventional device. Apart from this, the analysis shows a degradation of subthreshold swing (SS) and OFF current (IOFF) at elevated temperatures.

A novel source material engineered double gate tunnel field effect transistor for radio frequency integrated circuit applications

Tunnel field effect transistors (TFETs) have proved their potential for many possible electronic circuit applications. However, with the variety of TFET structures being worked upon it has been an unresolved challenge to optimize them for the applications to which they are best suited. In this paper we present a detailed comparative analysis of the linearity distortion and the radiofrequency (RF) performance parameters of a proposed heterojunction Mg2Si source double gate TFET (HMSDG-TFET) and a conventional homojunction Si source DG-TFET (SSDG-TFET). A source material engineering scheme is utilized to implement a staggered type 2 heterojunction at the source–channel junction by replacing the source material with Mg2Si (a low band gap material) to enhance the ON current (2.5 × 10–4 A µm−1), reduce the threshold voltage (0.26 V) and achieve a steeper subthreshold swing (10.05 mV decade−1). For linearity and distortion analysis, the figure of merit (FOM)-like higher-order transconductances, second- and third-order voltage intercepts, third-order intercept point, third-order intermodulation distortion, zero crossover point, 1 dB compression point, second-order harmonic distortion, third order harmonic distortion and total harmonic distortion have been examined. To portray the possible application of devices under consideration for RF integrated circuit applications, both structures are investigated for RF FOMs such as power gains, cutoff frequency (fT), maximum oscillation frequency (F max) and admittance parameters. Investigations carried out using a Silvaco ATLAS device simulator tool revealed that with fT approximately three orders higher (0.49 THz) and F max approximately two orders higher (0.9 THz) than that of a SSDG-TFET, the HMSDG-TFET is an appropriate candidate for use in high-frequency, high-linearity, low-distortion and low-power analog/RF applications.

Modeling and simulation of a dual-material asymmetric heterodielectric-gate TFET

Analytical modeling of a dual-material asymmetric heterodielectric-gate tunnel field-effect transistor (FET) is carried out based on the Poisson equation and parabolic approximation techniques. An asymmetric gate with two materials having different work functions is used to eliminate the influence of the OFF-current (leakage current) and short-channel effects in the device. The lengths of metal 1 and metal 2 are taken to be 10 nm and 10 nm, respectively, and the device performance is analyzed. Expressions for the surface potential, electric field, and drain current are obtained by using a two-dimensional (2D) mathematical model, whose results are compared with those obtained using the Silvaco technology computer-aided design (TCAD) simulator, revealing good agreement. The proposed dual-material asymmetric gate tunnel FET produces an improved ON-current of 10−5 A/µm and a decreased OFF current of 10−10 A/µm, with an ON/OFF ratio of 105.

Analytical model of a novel double gate metal-infused stacked gate-oxide tunnel field-effect transistor (TFET) for low power and high-speed performance

Abstract In this work, an innovative structure of a novel double gate tunnel field-effect transistor (TFET) is proposed with a channel length of 20 nm.The gate dielectric regions have been renovated by inserting metal strips and using stacked gate-oxide concept. The device exhibits suppressed ambipolar current, excellent subthreshold swing and good ION/IOFF ratio. The proposed structure proves to be a promising candidate for high speed applications as it shows lesser gate-capacitance than conventional stacked-oxide gate structure. The surface potential and electric field have been modelled considering the depletion regions, using 2-D Poisson's equation with appropriate boundary conditions, based on parabolic potential approximation. A semi-empirical method has been utilized to incorporate the effect of mobile charges on the device characteristics. A physics-based model for charge and terminal capacitances has been derived, following the potential model. The drain current model is able to accurately predict the ambipolar current as well as the effects of drain voltage in saturation region. Proper optimization of the device structure has been performed to derive the best desired electrical characteristics. SILVACO ATLAS simulation data have been used to validate the analytical results of the proposed structure, thereby corroborating the precision of the present analytical model. Finally, an inverter circuit has been designed in CADENCE circuit-simulation environment to justify the usage of our device in low power and high speed digital circuit applications.

Electrical performance of InAs/GaAs0.1Sb0.9 heterostructure junctionless TFET with dual-material gate and Gaussian-doped source

In this work, we demonstrate the design of a dual-material gate and Gaussian-doped source heterostructure junctionless tunnel field-effect transistor (DMG-GDS-HJLTFET). Unlike the conventional dual-material gate heterostructure junctionless tunnel field-effect transistor (DMG-HJLTFET), the proposed structure uses a Gaussian-doped source and adopts InAs/GaAs0.1Sb0.9 as a heterojunction at the source and channel interface, where a polarization electric field is induced by the lattice mismatch in the InAs and GaAs0.1Sb0.9 Zinc blende crystal. At the same time, the control gate electrode of the proposed structure is divided into two parts, namely tunnel gate (TG) and auxiliary gate (AG). In this structure, TG is located near the source side and has a lower work function, while AG is located near the drain side and has a higher work function, which not only improves ON-state current (Ion) but also decreases the OFF-state current. The performance of the proposed device is analyzed and compared with that of DMG-HJLTFET; simulation results show improvements in Ion, subthreshold swing, transconductance (gm), cut-off frequency (fT) and gain bandwidth (GBW). Compared with conventional DMG-HJLTFET, the maximum Ion and gm of the DMG-GDS-HJLTFET are 4.1 × 10−4 A μm−1 and 1.27 × 10−3 S μm−1 at 1.2 V gate-to-source voltage (Vgs); further, average subthreshold swing of DMG-GDS-HJLTFET is only 13.6 mV Dec−1 at low drain voltages. Also, DMG-GDS-HJLTFET could obtain a maximum fT of 193 GHz at Vgs = 0.8 V and a maximum GBW of 55.7 GHz at Vgs = 1.12 V, respectively.

Gate-tunable spin waves in antiferromagnetic atomic bilayers.

Remarkable properties of two-dimensional (2D) layer magnetic materials, which include spin filtering in magnetic tunnel junctions and the gate control of magnetic states, were demonstrated recently1-12. Whereas these studies focused on static properties, dynamic magnetic properties, such as excitation and control of spin waves, remain elusive. Here we investigate spin-wave dynamics in antiferromagnetic CrI3 bilayers using an ultrafast optical pump/magneto-optical Kerr probe technique. Monolayer WSe2 with a strong excitonic resonance was introduced on CrI3 to enhance the optical excitation of spin waves. We identified subterahertz magnetic resonances under an in-plane magnetic field, from which the anisotropy and interlayer exchange fields were determined. We further showed tuning of the antiferromagnetic resonances by tens of gigahertz through electrostatic gating. Our results shed light on magnetic excitations and spin dynamics in 2D magnetic materials, and demonstrate their potential for applications in ultrafast data storage and processing.

Photosensor Based on Split Gate TMD TFET Using Photogating Effect for Visible Light Detection

This paper reports a highly-sensitive and low power photosensor based on split gate tunnel field effect transistor (TFET) structure for visible light detection in wavelength ranging from 450-750 nm. The TFET based sensing device utilizes the photogating effect in a portion of transition metal dichalcogenide (TMD) channel. The optically tunable workfunction contrast between the two gates of dual material gate (DMG) TFET achieves significant gains in the overall device characteristics. It demonstrates high photo-to-dark current ratio of the order of 10 8 and variation in responsivity in the range between 10 3 AmW -1 to 10 -5 AmW -1 for V gs = -0.9 V. This paper further discusses the photodetector performance based on the position of the photogate on the tunneling or auxiliary side, the gate splitting ratio between the photosensing region and the metal, and the n-TFET based device design. The device performance has been analyzed using the analytical model for the optically controlled workfunction. This hybrid device consisting of an ultrathin channel sensitized with absorbing semiconductors while exploiting the characteristics of TFET leads to a new generation of highly sensitive photodetectors.