TFET Research Articles

First Demonstration of Vertical Sandwich GAA TFETs with Self-Aligned High-k Metal Gates and Abrupt Doping Tunneling Junctions

A new type of vertical sandwich gate-all around tunneling field-effect-transistors (TFETs), called VSATFETs, was demonstrated firstly with a CMOS-compatible process. The VSATFETs with self-aligned high-κ metal gates (HKMG) and abrupt doping tunneling junctions were fabricated with the epitaxial of p+−Si/i-SiGe/n+−Si sandwich structure and an isotropic quasi-atomic layer-etch (qALE) process. VSATFETs have the advantage of excellent control of channel size, because its gate-length is mainly determined by the thickness of SiGe film grown by epitaxy, and the diameter of the nanowires (NWs)/thickness of nanosheets (NSs) is determined by the qALE etching of SiGe selective to Si. A NW VSATFET with a diameter of 18 nm was fabricated and exhibits excellent characteristics: SSmin = 61.64 mV dec−1, Ion = 2.25 × 10−7 A u−1m−1 (@Vgs−Vt = 0.45 V, Vd = 0.65 V), Ion/Ioff = 1.81 × 106, DIBL = 7.58 mV. The effect of interface traps on the device performance was analyzed by the calibrated model. It is found that the device performance can be improved by decreasing the thickness/diameter of NS/NW TFET.

Improvements in reliability and radio frequency performance of junctionless tunnelling field effect transistor using p+ pocket and metal strip

AbstractIn this article, a new p+ pocket stacked gate oxide junctionless tunnelling field effect transistor (junction less tunnelling field effect transistor (JLTFET)) which has metal strip in gate oxide layer is proposed for analogue/RF circuit applications. Due to the insertion of a p+ pocket in source/channel junction and the use of metal strip in oxide layer, the following properties of the proposed JLTFET are resulted. First, the tunnelling barrier width is reduced in the source/channel junction thereby, electrons easily tunnel from the source to the channel. Second, the hole concentration (empty state) in the channel is increased, leading to higher electron contribution in the tunnelling process. These improvements are useful in achieving high drain current and steep subthreshold swing. As a result, the maximum ON current of 4.4 × 10−5 A/μm and average subthreshold swing of 40 mV/decade are obtained from simulation results. Moreover, as compared to conventional JLTFET, the proposed JLTFET provides improvements in reliability and analogue/radio frequency (RF) performance.

Role of Quasi-Fermi potential in modeling III-V TFETs: InAs as a case study

TFET accurate physically based models are highly required to analyze and predict the device characteristics for its future utilization in circuits. In order to precisely model TFETs, it is essential to understand the several aspects related to the physics-based modeling of these devices. Using 2D TCAD simulation, we showed that in order to appropriately model the electrostatic potential in InAs-based TFETs, the electron quasi-Fermi potential (eQFP) should be taken to depend on biasing conditions, both V DS and V GS , contrary to the case of Si-based TFETs in which the eQFP is considered independent of V GS which is widely encountered in the literature. The study is carried out for InAs double-gate homojunction tunnel FETs (DG-TFETs). In addition, we applied the main key factor of dependence of eQFP on a modified TFET model and it is revealed that the interpretation of eQFP correctly predicts the electrostatic potential and the drain-to-source band to band tunneling current.

A magnetically-induced Coulomb gap in graphene due to electron-electron interactions

Insights into the fundamental properties of graphene’s Dirac-Weyl fermions have emerged from studies of electron tunnelling transistors in which an atomically thin layer of hexagonal boron nitride (hBN) is sandwiched between two layers of high purity graphene. Here, we show that when a single defect is present within the hBN tunnel barrier, it can inject electrons into the graphene layers and its sharply defined energy level acts as a high resolution spectroscopic probe of electron-electron interactions in graphene. We report a magnetic field dependent suppression of the tunnel current flowing through a single defect below temperatures of ~2 K. This is attributed to the formation of a magnetically-induced Coulomb gap in the spectral density of electrons tunnelling into graphene due to electron-electron interactions.

Emerging 2D materials for tunneling field effect transistors

This work focuses on understanding the electronic properties of materials to enhance the performance of Tunnel Field Effect Transistor (TFET) through Density Functional Theory (DFT) simulations. Material selection prefers a p-type material with in-plane high density of state (DOS) (and low out-of-plane effective mass, m*, where defined for many layer systems), and high valence band maxima (VBM) energy stacked with an n-type material with low conduction band minimum (CBM) energy (large electron affinity (EA)) that creates a broken or nearly broken band alignment and has low lattice mismatch. SnSe2 is well-suited for an n-type 2D material due to high EA, while WSe2, Black phosphorous (BP) and SnSe are explored for p-type materials. Bilayers consisting of monolayers of WSe2 and SnSe2 show a staggered but nearly broken band alignment (gap of 24 meV) and a high valence band DOS for WSe2. BP-SnSe2 shows a broken band alignment and benefits from a low lattice mismatch. SnSe-SnSe2 shows the highest chemical stability, an optimal performance in terms of DOS of SnSe, tunability with an external field, and high VBM that also leads to a broken band alignment.

Investigation of heavy ion radiation and temperature on junctionless tunnel field effect transistor

Investigation of heavy ion radiation and temperature on junctionless tunnel field effect transistor

Polarized Tunneling Transistor for Ultrafast Memory

In today's information age, high performance nonvolatile memory devices have become extremely important. Despite their potential, existing devices suffer from limitations, such as low operation speed, low memory capacity, short retention time, and a complex preparation process. To overcome these limitations, advanced memory designs are required to improve speed, memory capacity, and retention time and reduce the number of preparation steps. Here, we present a nonvolatile floating-gate-like memory device based on a transistor that uses the polarization effect of ferroelectric material PZT (Pb[Zr0.2Ti0.8]O3) for regulating tunneling electrons for charging and discharging the MoS2 channel layer. The transistor is defined as a polarized tunneling transistor (PTT) and does not require a tunnel layer or a floating-gate layer. The PTT demonstrates an ultrafast programming/erasing speed of 25/20 ns and a response time of 120/105 ns, which is comparable to the ultrafast flash memories based on van der Waals heterostructures. Additionally, the PTT has a high extinction ratio of 104, a long retention time of 10 years, and a simple fabrication process. Our research provides future guidelines for the development of the next generation of ultrafast nonvolatile memory devices.

Machine learning-based output prediction of negative capacitance tunnel-FET

ABSTRACT Machine learning-based prediction of the output characteristics of a negative capacitance (NC) double gate (DG) Tunnel FET (TFET) (NC DG TFET) has been demonstrated in this paper. On current (ION), OFF current (IOFF) and sub-threshold slope (SS) have been predicted for different values of the body thickness (TSi), oxide thickness (TOX) and channel length (LCh) and the work function (WF). Random Forest Regression (RFR) model is used in the ML framework to explore the device characteristics. A total of 5444 simulated data has been generated by using the SILVACO ATLAS tool. After pre-processing the data, RFR-ML has been applied to obtain maximum accuracy. Root means square error (RMSE) (~0.34), R2 score (~0.965) and accuracy (~98.51%) parameter have been used as the figures of merit (FOM) to judge the efficiency of the proposed model with respect to the state-of-the-art literature. Besides, with higher accuracy, the model is capable of predicting the data within a few seconds compared to the few hundred hours using TCAD tools. This fast and accurate design strategy will surely be efficacious for the present VLSI industries.

Performance assessment of charge plasma based hetero‐structure VTFET biosensor for linearity enhancement

AbstractThis paper examines a charge plasma‐based hetero‐structure full gate vertical tunnel field effect transistor (CP‐FG‐VTFET) as a dielectrically modulated biosensor. It is also compared with a charge plasma‐based short gate vertical TFET (CP‐SG‐VTFET) biosensor and a charge plasma‐based asymmetrical vertical TFET (CP‐AS‐VTFET) biosensor with identical dimensions. We examine the basic physics of these biosensors and compare their ability to recognize charged and neutral molecules. It has been noted that these designs, which use GaSb as the n‐type TFET source material, are suitable for supply voltages lower than 1.2 V. The short gate device has a lower miller capacitance and a higher drive current because it has a narrow bandgap source material. Additionally, the left and right gate alignment of asymmetrical gate architectures has a considerable impact on the sensitivity of the device. Therefore, a simulation is conducted to assess the effects of gate misalignment on biosensor surface potential and drain current sensitivity. In addition, various figures of merits (FOMs) are computed for the device utilizing the dielectric constant range of 1–12, including linearity, sensitivity, and evaluation of noise characteristics. The widely available Silvaco TCAD was employed to simulate the proposed VTFET biosensors. A comprehensive evaluation of the FOM values showed that the CP‐FG‐VTFET is a promising device in terms of linearity and sensitivity.

Design and analysis of novel bilateral tunnelling based tunnel FET considering workfunction engineered metal strip for enhanced performance

Steep tunnelling junction is a crucial factor in nanometer regime tunnel field effect transistor (TFET) to achieve superior switching characteristics. In this regard, a novel architecture integrating low workfunction live metal strip (LWMS) in bilateral tunnelling based dual gate oxide TFET (BT DGO-TFET) is presented in this manuscript. This incorporation of LWMS results in generation of steep tunnelling junction at the channel source interface, which increases the electron accumulation, and thus boosts the tunnelling generation rate. Hence, the proposed structure accomplishes steep subthreshold swing, boosted ON-state current to OFF-state current ratio and decremented threshold voltage as compared to the conventional BT DGO-TFET. Apart from that, length, position and workfunction of LWMS has been optimized in order to achieve optimum device parameters. Finally, parameters of the proposed architecture have been compared with the parameters of the conventional BT DGO-TFET and TFETs in the existing literature. The proposed device is observed to be highly suitable for analogue/RF and low power switching applications.

Analysis of III-V material-based dual source T-channel junction-less TFET with metal implant for improved DC and RF performance

In this paper, two III-V material-based junctionless tunnel FET devices, D-1 and D-2, are proposed. The proposed device D-1 has a low bandgap (GaSb-based) dual source and a higher bandgap (GaAs-based) T-channel junctionless, and the proposed device D-2 has the same architecture as D-1 in addition to a metal strip implant in the gate oxide near both source regions. Due to junctionless architecture, the proposed D-1 and D-2 eliminate random dopant fluctuations (RDF), remove the need for high thermal budgeting, and give better performance with less variability. The wide bandgap (GaAs) T-channel and the drain region formed far from the gate fully suppress the ambipolarity for both the proposed D-1 and D-2. The low-bandgap GaSb material in the source improves the ON current for D-1 and D-2. Compared to the conventional junctionless TFET (JL-TFET), the proposed D-2 (even at a lower bias of 0.5 V) improves the ON current by 1.7 times and the ION/IOFF ratio by 216.66 times, with a much-reduced average subthreshold swing value of 32.7 mV/dec compared to 70 mV/dec of the conventional JL-TFET. Furthermore, the proposed D-2 also provides much improved RF performance with a higher transconductance (gm) of 147.8 μs, higher cut-off frequency (fT) of 32.26 GHz, a higher gain-bandwidth product (GBW) of 3.52 GHz, higher transconductance-frequency product (TFP) of 286 GHz, and a lower transit time (τ) of 5 × 10–12 s. Furthermore, we analyze various linearity parameters such as gm2, gm3, VIP2, VIP3, IIP3, and IMD3 for both D-1 and D-2, and our findings indicate that D-2 exhibits improved linearity performance.

Sensitivity analysis of Horizontal pocket N-TFET based biosensor considering repulsive steric effects

In this paper, sensitivity analysis of Tunnel Field Effect Transistor (TFET) based label free Biosensor has been countered considering the repulsive steric effect (RSE). Horizontal pocket based NTFET reference structure is being considered during ideal hindrance effect. Furthermore, the impact of RSE is considered to extract the capacitance, Drain current (ID), Energy Band Diagram, Surface Potential (ϕ), ION/IOFF ratio, tunneling rate, and ON current sensitivity (SION) for this biosensor. Moreover, sensitivity is being also measured by changing the position of the biomolecule with respect to source-channel interface. Later, noise assessment parameters like third order intercept point (IIP3), third order intermodulation point (IMD3), and low frequency analysis is observed to calculate the effect of noise during the hindrance effect. On Considering RSE effects, streptavidin biomolecules report an error in capacitance and surface potential are 39.60% and 12.3%, respectively. Finally, an error evaluation table is presented by considering the repulsive effects during the simulation. Therefore, the hindrance effect need to be considered for making the analysis label free and practical.

Investigation of single-event-transient effects on n+ pocket double-gate tunnel FET

This article investigates the response of double gate tunnel effect transistors (DG-TFETs) exposed to single-event effect (SEE) radiation. The radiation effects on different regions of DG-TFET are studied for various linear energy transfers (LETs) and drain voltages. The findings show that in both vertical and horizontal radiation, the channel and tunneling junction are the radiation-sensitive parts of DG-TFETs, respectively. To enhance radiation tolerance, an n + pocket is inserted at the source/channel junction to increase recombination and decrease the collected charges after irradiation. The results demonstrate that the n + pocket DG-TFET reduces the drain transient current peak under radiation by 23% compared to conventional DG-TFET. Furthermore, the incorporation of an n + pocket enhances the transistor's performance in multiple aspects. It not only reduces the subthreshold swing (SS) but also boosts the ON current (Ion) by a significant factor of 11 compared to the conventional DG-TFET.

An Analytical Approach to Study the Impact of Traps on Ge-Source Double Gate PNPN TFET

The analytical models for surface potential, electric field, and drain current of a Ge-source double gate hetero-structure PNPN Tunnel FET are developed taking into account the oxide-semiconductor interfacial trap charges. Although other researchers have used similar modeling techniques on various structures, the proposed structure has not yet utilized them when considering the source/drain depletion region and interfacial trap charges that reflect changes in the flat band voltage. The proposed device consists of Ge-source, Si1−xGex pocket (mole fraction 0.3), and Si channel and drain. Moreover, the non-uniform concentration of trap charges is considered at the oxide/semiconductor interfaces: 1013 cm−2 at HfO2/ Si1−xGex interface and 1012 cm−2 at HfO2/Si interface. 2D Poisson’s equation is solved with the help of parabolic potential approximation and different boundary conditions to develop the surface potential model. The developed potential model is subsequently used to construct the electric field model. The drain current model of the proposed TFET is finally developed with the help of the generated electric field and some other parameters. All the developed models are validated using TCAD-simulated data. The studies show that there is good agreement between the simulated and modeled results, ensuring the applicability of the device in charge-trapped memory systems based on tunneling.

Comparative Investigation of Different Doping Techniques in TMD Tunnel FET for Subdeca Nanometer Technology Nodes

Comparative Investigation of Different Doping Techniques in TMD Tunnel FET for Subdeca Nanometer Technology Nodes

Performance Boost of Si TFETs by Insertion of III–V Dipole Formation Layer: A First Principle Study

Silicon channel tunnel field-effect transistors (TFETs) are known to exhibit low ON-state current due to the wide indirect band gap. In this work, to achieve high ON-state current, we propose a Si TFET with an ultra-thin dipole formation layer (DFL) inserted at the source/channel junction. The inserted DFL forms charge transfer dipoles at the interface, resulting in a staggered band gap. As the consequence, the effective tunnel barrier for electrons is significantly lowered so that ON-state current increases by orders of magnitude. To analyze the characteristics of DFL-inserted Si TFETs, we have solved nonequilibrium Green’s function (NEGF) and Poisson’s equation using density functional theory (DFT) Hamiltonians. We demonstrate that DFL-inserted Si TFETs show boosted performance over conventional TFETs, exhibiting high ON-state current and steep subthreshold swing (SS).

Tunnel Field-Effect Transistor Triggered Silicon-Controlled Rectifier

In this article, a tunnel field-effect transistor (TFET) triggered silicon-controlled rectifier (SCR) device is proposed. A TFET is embedded into the SCR enabling an early carrier’s transportation through the n-well/p-well reverse-biased junction. This accelerates the junction breakdown and helps to establish the SCR’s positive feedback regeneration. The applications of the TFET-triggered SCR (TTSCR) in electrostatic discharge (ESD) protection are explored and the electrical characteristics are investigated. Moreover, the impact of the device structure on the device performance is discussed. The principle of the proposed device is verified using technology computer-aided design (TCAD) simulation. The simulation results show that compared to the prevalent diode-triggered SCR, the proposed device has a small layout area, a low leakage current, and a low overshoot voltage.

Designing and Reliability Analysis of Radiation Hardened Stacked Gate Junctionless FinFET and CMOS Inverter

Along with radiation sensing, necessity to study and design reliable radiation hardened devices is also increasing now-a-days. These devices are tolerant to high dosage of radiations without causing any physical damage, logic damage or data loss. In the current work, stacked gate Junctionless FinFET (SG JL FinFET) is analyzed as radiation hardened device by studying the impact of radiation of Linear Energy Transfer (LET) values ranging from 2MeV.cm/mg to 10MeV.cm/mg on the device performance. The proposed radiation hardened FinFET is experimentally calibrated with pre and post irradiation data. Single event upset (SEU) study using transient analysis is carried out to study the performance of proposed radiation hardened device at microwave frequency. High-k material-hafnium dioxide is used as gate oxide material to improve radiation hardness of SG JL FinFET. Electrical parameters-drain current, surface potential and SEU generation rate are studied to analyze device characteristics. Optimization of gate oxide, doping concentration, gate metals and temperature is carried out to enhance the reliability of device in terms of radiation hardness. SG JL FinFET is exposed to different types of waves-UV rays, X-ray, and Gamma rays to study the response of device at different frequencies. The comparison of SG JL and SG Inversion Mode (IM) FinFET has been performed. Comparison of SG JL FinFET with previously reported Inverted mode FinFET, L-shaped tunnel FET and Fully Depleted Silicon on Insulator (FD-SOI) MOSFET is carried out to find most suitable device which can provide highest immunity to radiation exposure. Response of JL FinFET based CMOS inverter in presence of radiation is studied and is also compared with other available CMOS inverters.

A high-performance doping-less tunnel FET with pocketed architecture: proposal and analysis

In this paper, we propose a doping-less dual-material double-gate tunnel field-effect transistor with a P+ pocket (PP-DMG TFET). This gate-engineered technique is typically used in a MOSFET to improve device performance. The P+ pocket is embedded at the source side to enhance the performance of the pocket-engineered PP-DMG TFET device. This paper compares the performance of four DG-TFET-based devices, i.e. single-material gate (SMG), single-material gate with P+ pocket (PP-SMG), dual-material gate (DMG), and dual-material gate with P+ pocket (PP-DMG), by using 2D simulations. Electrostatic doping based on the charge plasma concept forms the requisite n–i–p+ structure for tunneling formed on a thin intrinsic silicon layer. The proposed device (PP-DMG) has high ON-current capability, a high ON/OFF ratio and lower point subthreshold of 15.3 mV/dec, and an average subthreshold of 18.6 mV/dec. The analog parameters transconductance (gm) and cutoff frequency (fT) show impressive improvement. The device efficiency and transconductance frequency product (TFP) are also discussed. Finally, linearity and distortion analysis of parameters including VIP2, VIP3, IIP3, and IMD3 is carried out.

Undoped vertical dual-bilayer TFET with a super-steep sub-threshold swing: proposal and performance comparative analysis

In this paper, the undoped vertical dual-bilayer tunnel field effect transistor (UV-DBL-TFET) at a low operating voltage (0.5 V) is introduced, and its DC and RF performance parameters are compared with those of the conventional charge plasma-based symmetrical gate electron–hole bilayer TFET (CP-SG-EHBTFET). The charge plasma technique is used in the proposed device to induce the source/drain and electron–hole dual-bilayer channel dopants. Due to the dopingless architecture of the proposed UV-DBL-TFET, its fabrication is simple and efficient, and it does not require an expensive thermal annealing process. Due to its dopingless architecture, the proposed UV-DBL-TFET is immune against random dopant fluctuations. In the study, the quantum confinement effects in the TCAD simulation have been successfully modelled using the Schrodinger approach and the density gradient model. Compared to the conventional CP-SG-EHBTFET, the proposed UV-DBL-TFET has a dual EHB channel, triggers dual line tunnelling, and doubles the band-to-band tunnelling rate and the ON current. Compared to the I ON of 47.33 μA μm−1 and AVSS of 13.53 of the conventional CP-SG-EHBTFET, the proposed UV-DBL-TFET has almost double the ON current of 93.46 μA μm−1 with a reduced AVSS of 12.3 mV dec−1. The proposed UV-DBL-TFET also gives improved RF/analog performance. Compared to the transconductance (g m) of 0.337 mS, the cut-off frequency (f T) of 65.17 GHz, and the gain-bandwidth-product (GBW) of 16.5 GHz of the conventional CP-SG-EHBTFET, the proposed UV-DBL-TFET has a g m of 0.665 mS, a f T of 129.0 GHz, and an GBW of 32.6 GHz, an almost doubled improvement. Furthermore, the proposed UV-DBL-TFET-based CMOS inverter has also been comprehensively studied, and perfect complementary inverter action has been obtained, suggesting great potential for future low-power applications.