TFET Research Articles

Implementation and performance analysis of QPSK system using pocket double gate asymmetric JLTFET for satellite communications

This work is intended to design a quadrature phase shift keying (QPSK) system starting from the device design, characterization and optimization which is then followed by the circuit level implementation and finally the system level configuration. Tunnel Field Effect Transistor (TFET) technology came into existence because of the inability of CMOS (Complementary Metal Oxide Semiconductor) to produce reduced leakage current (Ioff) in the subthreshold regime. With the effects of scaling and requirement of high doping concentrations, TFET is not capable to produce stable reduction in Ioff due to the variation in ON and OFF current. To improve the switching ratio of the current and to obtain good subthreshold swing (SS) by overcoming the limitations of junction TFET, a new device design is proposed for the first time in this work. A pocket double gate asymmetric Junction less TFET (poc-DG-AJLTFET) structure has been proposed in which uniform doping is used to eliminate the junctions and a pocket of length 2 nm made of Silicon–Germanium (SiGe) material has been introduced to improve the designed structure performance in the weak inversion region and increase the drive current (ION). The work function has been tuned to produce the best results for poc-DG-AJLTFET and with our proposed poc-DG-AJLTFET, effects of interface traps are eliminated as against conventional JLTFET structures. The notion that low-threshold voltage device yields high IOFF has been proved wrong with our poc-DG-AJLTFET design, as it produced low threshold voltage with lower IOFF which reduced the power dissipation. Numerical results show that drain induced barrier lowering (DIBL) of 2.75 mV/V is achieved which could be less than 35 times required for short channel effects to be minimum. In terms of gate to drain capacitance (Cgd), it is found that ~ 103 reduction which greatly improves device inertia to internal electrical interference. Also, improvement in transconductance is achieved by 104 times, 103 times improvement in ION/IOFF ratio, and 400 times higher unity gain cutoff-frequency (ft) which would be required by all communication systems. The Verilog models of the designed device are used to construct the leaf cells of quadrature phase shift keying (QPSK) system and the implemented QPSK system is taken as a key evaluator in the performance evaluation in terms of propagation delay and power consumption of poc-DG-AJLTFET in modern satellite communication systems.

A novel high-low-high Schottky barrier based bidirectional tunnel field effect transistor

In this work, we proposed a novel High-Low-High Schottky barrier bidirectional tunnel field effect transistor (HLHSB-BTFET). Compared with previous technology which is named as High Schottky barrier BTFET (HSB-BTFET), the proposed HLHSB-BTFET requires only one gate electrode with independent power supply. More importantly, take an N type HLHSB-BTFET as an example, different from the previously proposed HSB-BTFET, due to that the effective potential of the central metal is increased with the increasing of drain to source voltage (Vds), built-in barrier heights maintain at the same value when the Vds is increased. Therefore, there is no strong dependence between built-in barrier heights formed in the semiconductor region on the drain side and the Vds. Besides that low Schottky barrier formed on the interface between the conduction band of silicon regions on its both sides and the central metal (while high Schottky barrier formed between the valence band of silicon regions on its both sides and the central metal) have been designed for preventing the carriers in valence band from flowing into the central metal induced by thermionic emission effect. Thereafter, the proposed N type HLHSB-BTFET has a natural blocking effect on the carriers flowing in valence band, and this blocking effect is not significantly degraded with the increasing of Vds, which is a huge promotion from the previous technology. The comparison between the two technologies is carried out, which exactly agrees with the design assumptions.

Design and Performance Analysis of a GAA Electrostatic Doped Negative Capacitance Vertical Nanowire Tunnel FET

Design and Performance Analysis of a GAA Electrostatic Doped Negative Capacitance Vertical Nanowire Tunnel FET

Investigation of Si 1−X GeX source dual material stacked gate oxide pocket doped hetero-junction TFET for low power and RF applications

ABSTRACT In this paper, the applicability of dual material stacked gate-oxide-Pocket doped-hetero-junction tunnel field effect transistor (DMSGO-PD-HTFET) for low power switching and radio frequency (RF) applications is investigated. In this context, gate workfunction engineering, the stacked-gate-oxide (+) approach, and asymmetrical doping at the P+ source () and N+ drain regions are considered. N+ pocket at source-channel interface implements DMSGO-PD-HTFET and improves interband tunnelling rate. This research aims to improve the device’s switching ratio (/), average subthreshold swing (), and radio frequency (RF) performance. For this, the control gate work function, mole fraction (X), pocket thickness, and doping concentration are optimised. Next, the DC, analog/RF and linearity figure of merits of the proposed device is analysed and the performance is compared with conventional all-silicon dual-material stack gate oxide tunnel field effect transistor (DMSGO-TFET) and dual-material stacked gate oxide-hetero-junction tunnel field effect transistor (DMSGO-HTFET) with source using technology computer-aided design (TCAD) device simulator. Based on the comparative analysis, the optimised design with exhibits an average subthreshold swing () of 28.8 mV/decade, switching ratio (/) of 2 × 1012, cut-off frequency () of 216 (GHz), and other significant improvements in analog/RF and linearity performance parameters. The proposed device is therefore suitable for switching and RF applications.

Study of ambipolar and linearity behavior of the misaligned double gate-drain dopant-free Nano-TFET: Design and performance enhancement

Work done in this article demonstrates the charge plasma based misaligned double gate-drain doping less tunnel field effect transistor. Designed devices such as perfectly aligned and misaligned, both are optimized by considering the secondary drain in order to investigate ambipolar and linearity behavior. As the work function of secondary drain increases reduction in the ambipolar current is observed with a little degradation in ON state current. It presents a tradeoff between ambipolar current and ON current hence suitable work function of secondary drain is necessary for the proper working of the device. Analog parameters such as ON current, ambipolar current, subthreshold slope, ON to OFF current ratio, ON current to ambipolar current ratio, threshold voltage are analyzed with respect to secondary drain. In order to investigate the device performance for low voltage and low noise applications various linearity parameters such as higher order transconductances, higher order harmonic distortions, higher order intermodulation point and transconductance gain factor have also been demonstrated all the designed structures. The values of ON current for perfectly aligned, underlap, overlap and both gate misaligned structure at 4.2eV of secondary drain work function is 52 μA, 30 μA, 18 μA and 12 μA respectively. And ambipolar current for perfectly aligned, underlap, overlap and both gate misaligned structure at 4.2eV of secondary drain work function is 3 pA, 23 pA, 247 pA and 705 pA respectively.

Comparison of low-dropout voltage regulators designed with line and nanowire tunnel-FET experimental data including a simple process variability analysis

This work presents the comparison between Nanowire Tunnel Field-Effect Transistor (NW-TFET) and Line-TFET applied on the design of Low-Dropout Voltage Regulator (LDO). Both devices have a SiGe source composition in order to enhance the current drive. The transistors were modeled using lookup tables (LUTs) approach based on experimental data using Verilog-A language. The LDOs were designed for two conditions, considering different gm/ID, load currents and load capacitances. In order to compare the TFET LDOs with an established technology, a MOSFET LDO was designed with TSMC 0.18 µm process design kit. Both TFET LDOs reach stability without the presence of a compensation capacitor. For gm/ID = 10.5 V−1 the current consumption of NW-TFET LDO (1.5nA) is near two orders of magnitude lower than Line-TFET LDO (68nA) and three orders of magnitude lower than MOSFET LDO (9 µA). The Line-TFET LDO exhibits better results in almost all parameters despite of the gain-bandwidth product (GBW) that is in the same order of magnitude of the MOSFET LDO, 171 kHz compared to 250 kHz for gm/ID = 10.5 V−1. The comparison between TFET LDOs for gm/ID = 7 V−1 was also performed regarding the transient and process variability analysis. The transient response revealed that the Line-TFET LDO has a pronounced lower settling time, 71 µs compared to 5 ms for a load step, but with a damped oscillatory response, the NW-TFET LDO presented lower undershoot for the load step. The process variability analysis was performed for devices within the wafer and was observed that the Line-TFET LDO suffers a higher impact with a 20 dB variation on the loop gain in comparison to 10 dB in the NW-TFET LDO.

Optical FOMs of extended-source DG–TFET photodetector in the visible range of the spectrum

In this paper, the optical characteristics of an extended-source double-gate tunnel field-effect transistor (ESDG–TFET)–based photodetector in the visible range of the spectrum at wavelength λ = (300–700) nm are investigated. The optical characteristics are examined at three specific wavelengths λ= 300, 500, and 700 nm at an intensity of 0.7 W cm−2. The optical characteristics of photosensors, such as absorption rate, generation rate, energy band profiles, transfer characteristics, sensitivity (S n), quantum efficiency (η), signal-to-noise ratio (SNR), and detectivity, are extracted according to the incident wavelength of light. The results reveal that the ESDG–TFET-based photosensor exhibits better optical characteristics at λ = 300 nm compared to at λ = 500 and 700 nm. Moreover, the proposed photosensor provides sensitivity, SNR, and responsivity in the order of 91.2, 79 (dB), and 0.74 (A Watt−1), respectively, at λ = 300 nm. Due to the high incident optical energy (E g) at 300 nm, the absorption and emission rates of this photosensor are significantly larger; consequently, it reports better optical characteristics. Finally, a comparative study of the proposed TFET-based photosensor with photosensors cited in the literature is summarized in tabular form. A comparison study in terms of spectral sensitivity between single-gate and double-gate ESDG–TFET is also reported. Moreover, an inverter circuit based on ESDG–TFET is designed, and the corresponding transient analysis is highlighted under both dark and light states.

Performance investigation of a charge plasma tunnel FET with SiGe source pocket as a photosensor

This study investigates a highly sensitive and low-power photosensor using a pocket-based charge plasma tunnel field-effect transistor (PCPTFET) structure for visible light detection. Here, zinc oxide, the transparent optical region over the channel, is the catalyst for the photo-sensing operation. When light strikes the sensitive portion of the device, creating optical charge carriers in the illumination region and substantially increases the device’s conductance. The analysis of various parametric and structural variations like intensity power density (Pj ), optical wavelength (λ), drain to source voltage (V DS), incident angle (θ), and silicon body thickness (t si) have been investigated for the reported pocket-based charge plasma TFET (PCPTFET) photosensor. Further, the PCPTFET’s superior performance as a highly sensitive photosensor is revealed by comparing the several optical figures of merit (FOM) with conventional tunnel field-effect transistor. The reported photosensor provides much-improved responsivity (R) of 1.52 A W−1 and quantum efficiency (η) of 4.96.

Sensing single domains and individual defects in scaled ferroelectrics.

Ultra-scaled ferroelectrics are desirable for high-density nonvolatile memories and neuromorphic computing; however, for advanced applications, single domain dynamics and defect behavior need to be understood at scaled geometries. Here, we demonstrate the integration of a ferroelectric gate stack on a heterostructure tunnel field-effect transistor (TFET) with subthermionic operation. On the basis of the ultrashort effective channel created by the band-to-band tunneling process, the localized potential variations induced by single domains and individual defects are sensed without physical gate-length scaling required for conventional transistors. We electrically measure abrupt threshold voltage shifts and quantify the appearance of new individual defects activated by the ferroelectric switching. Our results show that ferroelectric films can be integrated on heterostructure devices and indicate that the intrinsic electrostatic control within ferroelectric TFETs provides the opportunity for ultrasensitive scale-free detection of single domains and defects in ultra-scaled ferroelectrics. Our approach opens a previously unidentified path for investigating the ultimate scaling limits of ferroelectronics.

Optimization for Device Figure of Merit of Ferroelectric Tunnel FET using Genetic Algorithm

Tunnel FET is a gate-controlled, field effect transistor, followed band to band tunneling (BTBT) transport of charge carriers, having low subthreshold swing (SS < 60 Mv decade−1|T = 300 K). With tunnel FET, low-ION is a built-in problem, that limits its universal adaptability high-speed low-power uses. To overcome, this limitation of tunnel FET, a conventional double gate TFET has acquired for analysis having ferroelectric (BaTiO3)/HfO2 gate materials and source/channel region with Si1−xGex/Si semiconductor channel composition.The present device design techniques enhanced the ION and put down the subthreshold swing(SS). The analysis results by using the Silvaco simulator shows improvement in switching current(ION) approximately ∼103 times better than conventional DGTFET,without affecting the IOFF. Ultimately the change in ION∼order of 10−8 A μm−1 to 10−5 A μ has been measured for VDS ∼ 0.5 V at room temperature. The IOFF ( ∼10−20 A μm−1) has been measured. In addition to this, first time genetic algorithm has been used for the optimization of ferroelectric tunnel FET (Fe-Tunnel FET) device design parameters like a subthreshold swing (SS), ambipolar current (Iamb) and IONby using device deign parameters, doping (NS, ND), dielectric (εOX) and work function (WF).The research conclusion shows that Fe-Tunnel can play in lead backgroundfor super low power applications in advanced VLSI circuit and system.

Sensitivity and Stability Analysis of Double-Gate Graphene Nanoribbon Vertical Tunnel FET for Different Gas Sensing

Sensing and detecting gases are crucial from the application point of view. The essential condition for present-time gas sensors is light, compact, less power dissipation, highly sensitive, thermally stable, and a good selection regards several gases. Due to the significant potential and modulation of the energy bandgap, two-dimensional material has recently attracted researchers attention. Graphene nanoribbon (GNR) is one of the candidates from the two-D material; it is extracted from the strip of one-dimensional graphene material, which can be a suitable contender for gas sensing devices. Therefore, in this work, the detailed investigation of the gas sensor of various gas has been reported by employing two-dimensional material-based DG-GNR VTFET as a sensor. Different gases, including Oxygen, Ammonia as well as Hydrogen gas, have been scrutinized for sensitivity and stability in several temperature ranges. In the present work, several catalytic metals are utilized in the gate electrode of the proposed device architecture for the different gas sensing applications. The intrinsic physics of the proposed gas sensor has been carried out in detail in the factor of different gas molecules and gas pressure. Finally, the temperature parameter varies to analyze the stability of the proposed device sensor within 200 K–400 K.

Impact of Pocket Layer on Linearity and Analog/RF Performance of InAs-GaSb Vertical Tunnel Field-Effect Transistor

Impact of Pocket Layer on Linearity and Analog/RF Performance of InAs-GaSb Vertical Tunnel Field-Effect Transistor

Numerical assessment of dielectrically-modulated short- double-gate PNPN TFET-based label-free biosensor

A comprehensive investigation of dielectrically modulated Ge-source short double-gate PNPN tunnel FET (SG-PNPN TFET) based label-free biosensor is presented. Short gates and counter-doped pockets in the SG-PNPN TFET architecture improve band-to-band tunneling, which subsequently raises the device's drain current sensitivity. On the source side of the device, a nanocavity is created between the gate and the SiO2 layer. The sensing performance of the device was evaluated using the effect of the dielectric constant and charge density of the biomolecules. The non-ideal performance of the biosensor can be understood by analyzing the consequences of steric hindrance and irregular probe placement. The concave profile has the highest value of sensitivity among all the non-uniform profiles considered (including ascending, descending, concave, and convex). The sensitivity comparison of the proposed TFET biosensor with other FET-based biosensors revealed that the SG-PNPN TFET could function admirably as a low-power biosensor with improved sensitivity.

Study on the Simulation of Biosensors Based on Stacked Source Trench Gate TFET.

In order to detect biomolecules, a biosensor based on a dielectric-modulated stacked source trench gate tunnel field effect transistor (DM-SSTGTFET) is proposed. The stacked source structure can simultaneously make the on-state current higher and the off-state current lower. The trench gate structure will increase the tunneling area and tunneling probability. Technology computer-aided design (TCAD) is used for the sensitivity study of the proposed structured biosensor. The results show that the current sensitivity of the DM-SSTGTFET biosensor can be as high as 108, the threshold voltage sensitivity can reach 0.46 V and the subthreshold swing sensitivity can reach 0.8. As a result of its high sensitivity and low power consumption, the proposed biosensor has highly promising prospects.

Ultrasensitive Strain Sensor Based on a Tunnel Junction with an AlN/GaN Core-Shell Nanowire

Piezotronic transistor operating in the quantum tunneling regime has recently roused wide interest for developing ultrasensitive strain sensing with applications in wearable electronics and human-machine interfaces. However, the lack of a strict theoretical demonstration from a quantum perspective renders the development of such an emerging area particularly slow due to their complex fabrication process and vulnerable experimental interference. Here, by combining third-dimensional self-consistent calculation with a nonequilibrium Green's function framework, we study the intrinsic device properties of piezotronic tunneling transistor (PTT) based on $\mathrm{Al}\mathrm{N}/\mathrm{Ga}\mathrm{N}$ core-shell nanowire. The results show that strain-induced piezoelectric polarization can remarkably tune tunneling barrier height and width, both of which are increased by tensile strain and decreased by compressive strain. At a moderate strain amplitude of 1.0% and bias of 2.0 V, the strain-induced change in effective barrier height and width can reach as high as 0.5 eV and 4.0 nm, respectively. This remarkable tunability in the barrier allows for an ultrahigh on/off current ratio ${10}^{17}$, and giant gauge factor 1.2 \ifmmode\times\else\texttimes\fi{} ${10}^{8}$ in current and 1.1 \ifmmode\times\else\texttimes\fi{} ${10}^{13}$ in resistance. The performance can be further optimized by properly tailoring device architectures, including insulator thickness, nanowire length, or core-shell size. Our demonstration of the PTT with combined quantum tunneling and piezotronic effect opens a window for designing highly sensitive, large on/off ratio and low-power strain sensing.

Controlling Drain Side Tunneling Barrier Width in Electrically Doped PNPN Tunnel FET

In this paper, we propose and investigate an electrically doped (ED) PNPN tunnel field effect transistor (FET), in which the drain side tunneling barrier width is effectively controlled to obtain a suppressed ambipolar current. We present that the proposed PNPN tunnel FETs can be realized without chemically doped junctions by applying the polarity bias concept to a doped N+/P- starting structure. Using numerical device simulations, we demonstrate how the tunneling barrier width on the drain side can be influenced by several design parameters, such as the gap length between the channel and the drain (Lgap), the working function of the polarity gate, and the dielectric material of the spacer. The simulation results show that an ED PNPN tunneling FET with an ED drain, which has been explored for the first time, exhibits a low ambipolar current of 5.87 × 10-16 A/µm at a gap length of 20 nm. The ambipolar current is reduced by six orders of magnitude compared to that which occurs with a conventional ED PNPN tunnel FET with a uniformly doped drain, while the average subthreshold slope and the ON state and OFF state currents remained nearly identical.

Modeling and Performance Analysis of a Split-Gate T-Shape Channel DM DPDG-TFET Label-Free Biosensor

This article proposes, for the first time, a split-gate T-shape channel dielectrically modulated (DM) double-gate TFET (DGTFET) with a drain pocket (DP). This device can be used as a label-free biosensor. The analytical model for DM DPDG-TFET has been developed and it has been validated against commercial simulation software (Silvaco TCAD). This article intends to focus both on the sensitivity of the biosensor and its performance as a tunnel field-effect transistor (TFET) device. This has been accomplished by improvisations in the channel shape. The performance of the device has thoroughly been investigated in terms of threshold voltage, subthreshold slope, ON current, and OFF current. Due to the novel design, the proposed TFET possesses higher sensitivity, higher <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{ {\text{ON}}}/{I}_{ {\text{OFF}}}$ </tex-math></inline-formula> current ratio, and lower subthreshold slope. The inclusion of DP at the drain–channel junction proves to be a successful way to remove the ambipolarity completely. The high ON current without any ambipolarity has been achieved by optimizing the DP length and its doping concentration. The proposed T-shape DM DPDGTFET proves itself to be superior to several reported devices in terms of both biosensor as well as field-effect transistor (FET) device. The presence and absence of charge of various biomolecules are taken into consideration for evaluation of device sensitivity as a label-free biosensor.

Multi-state tunnel field effect transistor based on face tunneling with gate-source overlap

In this paper, a ternary surface tunneling field effect transistor (TF-TFET) based on the tunneling mechanism is designed and fabricated. By adjusting the parameters and bias voltage of the surface tunneling and the line tunneling, the transistor introduces a stable ”intermediate state” between the switching states of conventional binary TFET devices, which realizes the function of a ternary logic device. The device can realize the conversion of ternary logic and binary logic devices under certain conditions, and realize various functions. The fabrication process of the device is compatible with the traditional CMOS process and is also of great significance for realizing the development of the ternary logic operation unit.

A new analytical modelling of 10 nm negative capacitance-double gate TFET with improved cross talk and miller effects in digital circuit applications

In this paper, the workability of a Negative Capacitance (NC)-Double Gate (DG) Tunnel FET (NC-DGTFET) for digital logic circuit implementation has been detailed. New analytical modelling of the drain current of the NC-DGTEFT considering the band to band tunneling (BTBT), Band tail tunneling (BTT) and Source drain tunneling (SDT) have been investigated. Significant IOÑ0.025 μA/μm at 250 mV and SS∼12mv/dec - 22mv/dec with very low IOFF (∼fA/μm) is observed with the optimized device. SILVACO ATLAS and MATLAB have been used to validate the proposed model. The modeled NC-DGTFET based Inverter, NAND/NOR has been implemented and the power, delay propagation, and the power delay product (PDP) of the circuit have been analyzed to show the energy efficacy of the NC-DGTFET in the sub-threshold regime (STR) with respect to baseline TFET (B-TFET). To evaluate the impact of the Miller's effects on the digital performances, NC-DGTFET-based five stages Inverter with Fanout = 1 is considered a device under test (DUT) here. Peak overshoot voltage and delay for different fanout and ferroelectric thickness are detailed to show the efficacy of the proposed logic circuits in sub-threshold regime. Both the cross talk and the Miller effects are mitigated significantly in the NC-DGTFET-based digital circuits.

Investigation of a dual gate pocket-doped drain engineered tunnel FET and its reliability issues

Investigation of a dual gate pocket-doped drain engineered tunnel FET and its reliability issues