Triple Reduced Surface Field Research Articles

Process and performance optimization of Triple‐RESURF LDMOS with Trenched‐Gate

In this article, we investigate by TCAD simulation, the combination triple reduced surface field (triple-RESURF) and trenched-gate to design an n-type laterally diffused metal-oxide-semiconductor (LDMOS) transistor with high performance. While similar structures reported in the literature, on the one hand, use either the triple-RESURF or trenched-gate at once, on the other hand, those features require at least one additional mask each. We have been able to achieve both features in one transistor with only eight masks at the front-end of line (FEOL), and one less annealing. Therefore, our proposition will be cheaper and provide better performance. The structure is obtained by re-organizing the process steps, re-using other existing masks, and exploiting positive and negative photoresist photolithography. The resulting specific on-state resistance (RON,SP) is 94 mΩmm2, and the breakdown voltage (BV) is 71 V. But, most importantly a high transconductance (gm) at high gate voltages, with acceptable off-state leakage current (Ioff), which translates into better RF performance overall than what is reported in the literature. The maximum oscillation frequency (fMAX) and cut-off frequency (fT) could reach up to 76 and 43 GHz, respectively. Our device targets fully integrated IoT ASICs that require power amplifiers.

Analytical Study on a 700 V Triple RESURF LDMOS With a Variable High-K Dielectric Trench

A novel 700 V triple REduced SURface Field (RESURF) lateral double-diffused MOSFETs (LDMOS) with a variable high- K (VHK) dielectric trench for smart power applications is proposed and studied by TCAD simulations. Compared with conventional triple RESURF (CTR) LDMOS, the new structure features a composite high- K (HK) dielectric trench embedded in the drain edge. First, a higher HK dielectric layer is in the upper trench to suppress the high electric field ( E-field) under the drain by dielectric RESURF. Second, a lower HK dielectric is at the bottom of the trench to promote the depletion of the N-buffer layer and P-substrate, which increases the N-buffer doping concentration and thus reduces ON-resistance. The overall vertical bulk E-field distribution is modulated by the E-field peak generated at the position of varying K dielectric, which greatly improves breakdown voltage (BV). An analytical model of BV and vertical E-field taking account of the influence of the VHK dielectric trench is presented. Simulation results show that the proposed VHK TR LDMOS is able to obtain a 30.2% higher BV and a lower 15.4% R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON, sp</sub> than the CTR LDMOS. Moreover, the figure of merit (BV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON,sp</sub> ) of VHK TR LDMOS has doubled further breaking the lateral silicon limit.

Theoretical study on optimization criterion of the triple RESURF lateral power devices via virtual junction concept

The triple reduced surface field (T-RESURF) technique allows the drift region to achieve a much higher doping concentration while maintaining its breakdown voltage unaffected. Yet, as a result of the missing design guidance, the optimization of the T-RESURF effect is difficult to be realized in practice. In light of that, in this paper, the Virtual Junction Concept is proposed to provide the optimization criterion and explore physical insight of the T-RESURF effect. The proposed method bypasses the complicated 2D analysis by equivalenting the 2D drift region to a 1D virtual junction. The effectiveness and correctness of such a method are validated by the good agreement between modeled and simulated results. Benefit from its simplicity and veracity, the proposed method can not only conduct qualitative and quantitative analysis on the T-RESURF effect but also capable of providing design guidance and optimization criterion.

A Novel Ultralow R ON,sp Triple RESURF LDMOS With Sandwich n-p-n Layer

This article proposes a novel ultralow specific ON-resistance (RON,sp) triple reduced surface field (RESURF) lateral double-diffused MOSFET (LDMOS) with sandwich np-n layer. Compared with the conventional triple RESURF LDMOS with n-type top layer (NTTR LDMOS), the new structure is characterized by an additional N-buried layer below the P-buried layer. Due to the introduction of N-buried layer, the concentration of N-top layer will decrease to ensure charge balance, thus making the surface electric field distribution better and the higher additional doping introduced by N-top and N-buried layers can be achieved. The dose and implantation energy of n-p-n layers were simulated and optimized. Furthermore, in order to eliminate the premature avalanche breakdown occurring in the source-centered termination region, substrate termination technology (STT) is applied to avoid the high electric field peaks generated in the curved source region with small curvature radius. But the use of STT makes it easy to breakdown in the transitional region compared with the straight region. Therefore, the transitional region is studied and the crucial parameter AL in the layout of transitional region is also optimized. The fabricated device experimentally demonstrated improved performance with low R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON,sp</sub> of 78.3 mΩ·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and high breakdown voltage (BV) of 795 V, and the experimental R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON,sp</sub> is 26.8% lower than that of the conventional triple RESURF LDMOS (CTR LDMOS) and 10% lower than that of the NTTR LDMOS based on L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> = 67 μm, which can break the silicon limit of CTR and NTTR LDMOS and meet the demand of 700-V high-voltage integrated circuit applications.

Novel Homogenization Field Technology in Lateral Power Devices

A novel Homogenization Field Technology (HOFT) in lateral power devices is proposed and experimentally proved in this letter. By introducing the periodically discrete metal insulator semiconductor (MIS) structure, which realizes periodic equal potential and self-charge balance, the HOFT obtains almost uniform surface and bulk electric field distributions in the voltage sustaining layer. Therefore, the new device harvests both higher breakdown voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> and lower specific on-resistance R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> than those of the conventional reduced surface field (RESURF) technology in much higher and wider doping dose range. The experiment of the HOFT device realized a V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> of 672 V and a R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> of 56.7 mΩ · cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> under a high doping dose of 5.6 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> , which represents a reduction of 33.8% when compared with the theoretical value of the triple RESURF technology.

Triple Reduced Surface Field Drain Extended MOS Device Design and Its RF Performance Evaluation for Sub-Micron RF SoC Platform

Triple Reduced Surface Field Drain Extended MOS Device Design and Its RF Performance Evaluation for Sub-Micron RF SoC Platform

PSOI pLDMOS with n‐buried layer

Partial-silicon (Si)-on-insulator p-channel lateral double-diffused metal–oxide–semiconductor field-effect transistor with n-buried layer (NBL PSOI pLDMOS) is proposed. One feature of the device is an Si window under the drain offers a heat conduction path to alleviate the self-heating effect. Meanwhile, a fully depleted NBL on the bottom surface of the Si layer provides a large amount of ionised donors to enhance the electric field of the buried oxide (BOX) layer. The NBL can prevent the substrate leakage phenomenon of the PSOI pLDMOS. There is a triple reduced surface field structure in the p-drift region. Some equipotential lines spread into the p-substrate through the Si window. Furthermore, the assistant depletion caused by the NBL increases the p-drift region concentration, which achieves a lower specific on-resistance (R on,sp). With 20 µm p-drift region length and 1 µm BOX thickness, the NBL PSOI pLDMOS obtains a higher breakdown voltage (BV) of 289 V, which is increased by 88.9 and 43.8% compared with the Con SOI and NBL SOI pLDMOS, respectively. The R on,sp is decreased by 82.3 and 17.2%, respectively. The figure of merit (FOM = BV2/R on,sp) is 1.65 MW cm−2. A lower maximum surface temperature of 312.3 K is obtained.

Optimized Dynamic $\text{R}_{ \mathrm{\scriptscriptstyle ON}}$ With p-Type Buried Layer Bridge in 700-V Triple RESURF nLDMOS

The dynamic on-resistance ( $\text{R}_{ \mathrm{\scriptscriptstyle ON}}$ ) problem widely exists in reduced surface field (RESURF) lateral DMOS (LDMOS), which leads to large conduction losses in the switching application. Analysing a 700-V triple RESURF LDMOS, the mechanism of this phenomenon is researched by the analytical model and the experimental results. Building some bridges of the p-type buried layer (Pbury), the charges of the Pbury-N-well capacitance are discharged. The $\text{V}_{\mathrm {{ds}}}$ can be reduced to the static value quickly without the tail. Therefore, the dynamic $\text{R}_{ \mathrm{\scriptscriptstyle ON}}$ is significantly reduced. Meanwhile, the breakdown voltage is not affected by the Pbury bridge.

3-D Edge Termination Design and ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ -BV Model of A 700-V Triple RESURF LDMOS With N-Type Top Layer

3-D edge termination design and analytic model for specific on-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}})$ versus breakdown voltage (BV) of a 700-V triple reduced surface field lateral double-diffused MOSFET (LDMOS) with n-type top layer are presented in this paper. To eliminate the premature avalanche breakdown induced by the electric field crowding and the local charge imbalance in the transition region of the source-centered edge termination structure, 3-D numerical simulations and experiments are performed to investigate two crucial parameters ${L}_{1}$ and ${L}_{2}$ in the layout of the transition region. It is observed that optimal electric field distribution is obtained and breakdown positions are transferred to the active region at ${L}_{1} = 30~\mu \text{m}$ and ${L}_{2} = 1~\mu \text{m}$ . On the other hand, an analytic model is developed to describe the relation between ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ and BV, which is obtained as ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}} = 5.93 \times 10^{-6} \times 22({T}/298)^{1.7} \times \text {BV}^{2}$ and theoretically verifies that the fabricated device has achieved optimized ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ and BV. Compared with our previous paper, the LDMOS experimentally demonstrated improved performance with ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ of 86.49 $\text{m}\Omega ~\cdot $ cm2 and BV of 805 V, which is leading performance for the 700-V applications in published data.

Design of a novel triple reduced surface field LDMOS with partial linear variable doping n-type top layer

A novel triple reduced surface field (RESURF) lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS) with partial linear variable doping (LVD) N-type top (N-top) layer is proposed in this paper. Compared with the conventional triple RESURF LDMOS, a partial LVD N-top layer is introduced in the surface of N-well, providing a low on-resistance conduction path and leading to an optimized surface electric field, which alleviates the inherent tradeoff between the breakdown voltage (BV) and specific on-resistance (Ron,sp). With the n-drift region length of 70 μm, the novel triple RESURF LDMOS obtains a high BV of 847 V and a low Ron,sp of 79 mΩ cm2 which are 76 V higher and 46 mΩ cm2 lower than those of the conventional triple RESURF LDMOS. Therefore, the novel triple RESURF LDMOS can greatly improve the tradeoff between BV and Ron,sp. Furthermore, compared with the other existing technologies in the high BV level, the novel triple RESURF LDMOS can achieve a highest figure of merit (FOM, defined as BV2/Ron,sp) of 9.08 MW/cm2 and the conventional RESURF silicon limits are broken.

Modeling of a triple reduced surface field silicon-on-insulator lateral double-diffused metal–oxide–semiconductor field-effect transistor with low on-state resistance**Project supported by the National Natural Science Foundation of China (Grant No. 61376080), the Natural Science Foundation of Guangdong Province, China (Grant No. 2014A030313736), and the Fundamental Research Funds for the Central Universities, China (Grant No. ZYGX2013J030).

An analytical model for a novel triple reduced surface field (RESURF) silicon-on-insulator (SOI) lateral double-diffused metal–oxide–semiconductor (LDMOS) field effect transistor with n-type top (N-top) layer, which can obtain a low on-state resistance, is proposed in this paper. The analytical model for surface potential and electric field distributions of the novel triple RESURF SOI LDMOS is presented by solving the two-dimensional (2D) Poisson’s equation, which can also be applied to single, double and conventional triple RESURF SOI structures. The breakdown voltage (BV) is formulized to quantify the breakdown characteristic. Besides, the optimal integrated charge of N-top layer (Qntop) is derived, which can give guidance for doping the N-top layer. All the analytical results are well verified by numerical simulation results, showing the validity of the presented model. Hence, the proposed model can be a good tool for the device designers to provide accurate first-order design schemes and physical insights into the high voltage triple RESURF SOI device with N-top layer.

Analytical Modeling for a Novel Triple RESURF LDMOS With N-Top Layer

An analytical model for a novel triple reduced surface field (RESURF) lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistor with a low on-resistance n-type top (N-top) layer is proposed in this paper. The analytical model for surface potential and electric field distributions of the novel triple RESURF LDMOS is presented by solving the 2-D Poisson's equation, which can also be applied in single, double, and conventional triple RESURF structures. The vertical and lateral breakdown voltages are formulized to quantify the breakdown characteristic. Besides, the optimal integrated charge of the N-top layer (Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ntop</sub> ) is derived which can give a guidance for the dose of N-top layer. The triple RESURF LDMOS with a low on-resistance N-top layer is designed and manufactured according to the analytical model. All the analytical results can be well verified by numerical and measured results, showing the validity of the presented model.

A 800 V dual conduction paths segmented anode LIGBT with low specific on-resistance and small shift voltage

A dual conduction paths segmented anode lateral insulated-gate bipolar transistor (DSA-LIGBT) which uses triple reduced surface field (RESURF) technology is proposed. Due to the hybrid structures of triple RESURF LDMOS (T-LDMOS) and traditional LIGBT, firstly, a wide p-type anode is beneficial to the small shift voltage (VST) and low specific on-resistance (Ron,sp) when the anode voltage (VA) is larger than VST. Secondly, a wide n-type anode and triple RESURF technology are used to get a low Ron,sp when VA is less than VST. Meanwhile, it can accelerate the extraction of electrons, which brings a low turn-off time (Toff). Experimental results show that: VST is only 0.9 V, Ron,sp (Ron × Area) are 11.7 and 3.6 Ω·mm when anode voltage VA equals 0.9 and 3 V, respectively, the breakdown voltage reaches to 800 V and Toff is only 450 ns.

A low on-resistance triple RESURF SOI LDMOS with planar and trench gate integration

A low on-resistance (Ron,sp) integrable silicon-on-insulator (SOI) n-channel lateral double-diffused metal-oxide-semiconductor (LDMOS) is proposed and its mechanism is investigated by simulation. The LDMOS has two features: the integration of a planar gate and an extended trench gate (double gates (DGs)); and a buried P-layer in the N-drift region, which forms a triple reduced surface field (RESURF) (TR) structure. The triple RESURF not only modulates the electric field distribution, but also increases N-drift doping, resulting in a reduced specific on-resistance (Ron,sp) and an improved breakdown voltage (BV) in the off-state. The DGs form dual conduction channels and, moreover, the extended trench gate widens the vertical conduction area, both of which further reduce the Ron,sp. The BV and Ron,sp are 328 V and 8.8 mΩ·cm2, respectively, for a DG TR metal-oxide-semiconductor field-effect transistor (MOSFET) by simulation. Compared with a conventional SOI LDMOS, a DG TR MOSFET with the same dimensional device parameters as those of the DG TR MOSFET reduces Ron,Sp by 59% and increases BV by 6%. The extended trench gate synchronously acts as an isolation trench between the high-voltage device and low-voltage circuitry in a high-voltage integrated circuit, thereby saving the chip area and simplifying the fabrication processes.

Novel SOI double-gate MOSFET with a P-type buried layer

An ultra-low specific on-resistance (Ron,sp) integrated silicon-on-insulator (SOI) double-gate triple RESURF (reduced surface field) n-type MOSFET (DG T-RESURF) is proposed. The MOSFET features two structures: an integrated double gates structure (DG) that combines a planar gate with an extended trench gate, and a p-type buried layer (BP) in the n-type drift region. First, the DG forms dual conduction channels and shortens the forward current path, so reducing Ron,sp. The DG works as a vertical field plate to improve the breakdown voltage (BV) characteristics. Second, the BP forms a triple RESURF structure (T-RESURF), which not only increases the drift doping concentration but also modulates the electric field. This results in a reduced Ron,sp and an improved BV. Third, the extended trench gate and the BP linked with the p-body region reduce the sensitivity of the BV to position of the BP. The BV of 325 V and Ron,sp of 8.6 m Ω·cm2 are obtained for the DG T-RESURF by simulation. Ron,sp of DG T-RESURF is decreased by 63.4% in comparison with a planar-gate single RESURF MOSFET (PG S-RESURF), and the BV is increased by 9.8%.