Novel SOI double-gate MOSFET with a P-type buried layer

Abstract

An ultra-low specific on-resistance (Ron,sp) integrated silicon-on-insulator (SOI) double-gate triple RESURF (reduced surface field) n-type MOSFET (DG T-RESURF) is proposed. The MOSFET features two structures: an integrated double gates structure (DG) that combines a planar gate with an extended trench gate, and a p-type buried layer (BP) in the n-type drift region. First, the DG forms dual conduction channels and shortens the forward current path, so reducing Ron,sp. The DG works as a vertical field plate to improve the breakdown voltage (BV) characteristics. Second, the BP forms a triple RESURF structure (T-RESURF), which not only increases the drift doping concentration but also modulates the electric field. This results in a reduced Ron,sp and an improved BV. Third, the extended trench gate and the BP linked with the p-body region reduce the sensitivity of the BV to position of the BP. The BV of 325 V and Ron,sp of 8.6 m Ω·cm2 are obtained for the DG T-RESURF by simulation. Ron,sp of DG T-RESURF is decreased by 63.4% in comparison with a planar-gate single RESURF MOSFET (PG S-RESURF), and the BV is increased by 9.8%.