Tri-gate MOSFETs Research Articles

Analytical subthreshold current model of the dual-material tri-gate (DMTG) MOSFET and its application for subthreshold logic gate

Multi-gate MOSFETs are considered for realizing ultra-low-power circuits due to their superior channel control capability and short channel effect (SCE) resistance. To achieve this goal, it is necessary to establish a suitable compact device circuit model for them. However, current research focuses more on single-material multi-gate MOSFET, and there is no research report on dual-material logic gates. In this work, we develop a subthreshold current model for dual-material tri-gate (DMTG) MOSFET. It is found that the gate metal close to the source can affect the subthreshold characteristics of the transistor to a greater extent. Moreover, combined with the equivalent transistor model, the noise margin (NM) model of the subthreshold inverter composed of DMTG MOSFETs is developed. The nearly equal NM can be obtained by equal NM design (END). An appropriate work function can be selected through END to obtain the optimal NM when designing the inverter. The NM under different device geometric parameters is given, and the simulation result shows that the model accuracy reaches 98%. Finally, the effect of DMTG structure on the device drain induced barrier lowering (DIBL) is given, which effectively reduces DIBL by 42%. These models still remain high accuracy when the device channel length shrink down to 20 nm, which provide the possibility for DMTG MOSFET to be effectively applied to ultra-low-power circuits.

Analysis of Multi Bridge Channel Undoped Trigate MOSFET by Different High-k Dielectrics for Sub 10 nm

Analysis of Multi Bridge Channel Undoped Trigate MOSFET by Different High-k Dielectrics for Sub 10 nm

The Tri-Gate MOSFET: A New Vertical Power Transistor in 4H-SiC

The tri-gate MOSFET is a vertical power transistor with multiple sub-micron FinFET channels. The FinFET structure increases the current-carrying width of the MOS inversion layer without increasing the device area, thereby reducing the specific channel resistance. This is especially useful in silicon carbide where the inversion layer mobility is ~10× lower than in silicon. This innovation can reduce the on-resistance of SiC power MOSFETs at blocking voltages below 1,000 V where over 68% of the applications lie.

Gate Work Function Engineered Trigate MOSFET with a Dual-Material Bottom Gate for Biosensing Applications: a Dielectric-Modulation Based Approach

Mathematical model development of a Dielectric-Modulated Dual Material Trigate MOSFET with a dual material bottom gate has been introduced for application as a biosensor for detection of biomolecules like enzymes, cell, DNA etc. With solution of 3-D Poisson’s equation, electrical features of the proposed device have been acquired and corresponding shift in the device features due to change in permittivity, charge etc. by the biomolecules implies the type of biomolecule introduced in the nanogap. Further simulation results from Atlas corroborate the analytical results.

Analytical modelling and performance analysis of gate‐ and channel‐engineered trapezoidal trigate MOSFET

Here, the authors propose an analytical model to evaluate the performance of an advanced trigate MOSFET structure called trapezoidal trigate MOSFET on silicon-on-nothing (TTMSON). The model is based on the solution of Poisson's partial differential equation in three dimensions. The expression for potential distribution has been used to model other device parameters like electric field distribution, quantum inversion charge, and threshold voltage. The TTMSON device immunity to various short channel effects (SCEs), such as drain-induced barrier lowering (DIBL) and sub-threshold swing, has been examined. A detailed analysis of the gate and channel engineering techniques like dual material gate, graded channel, and dual material gate with graded channel has also been carried out to choose the best device structural configuration for enhancing the device performance and mitigating SCEs in nano-regime. In addition, the effect of inclination angle on different performance parameters has been considered. The proposed analytical model of TTMSON has been verified by comparing the model results with the simulation results using the numerical device simulator ATLAS.

High-Voltage Normally-off Recessed Tri-Gate GaN Power MOSFETs With Low on-Resistance

In this letter, we present normally-off GaN-on-Si MOSFETs based on the combination of tri-gate with a short barrier recess to yield a large positive threshold voltage ( ${V}_{\text {TH}}$ ) while maintaining a low specific on resistance ( R $_{ON, \text {SP}}$ ) and high current density ( ${I}_{\text {D}}$ ). The tri-gate structure offered excellent channel control, enhancing ${V}_{\text {TH}}$ from +0.3 V for the recessed to +1.4 V for the recessed tri-gate, along with a much reduced hysteresis in ${V}_{\text {TH}}$ , and a significantly increased transconductance ( ${g} _{\text {m}}$ ). Additional conduction channels at the sidewalls of the tri-gate trenches compensated the degradation in ON-resistance ( ${R} _{ON}$ ) from the gate recess, resulting in a small ${R} _{ON}$ of $7.32~\pm ~0.26~\Omega \cdot $ mm for ${L} _{\text {GD}}$ of $15~ {\mu }\text{m}$ and an increase in the maximum drain current ( ${I}_{\text {D}}^{\text {max}}$ ). In addition, the tri-gate inherently integrates a gate-connected field-plate (FP), which improved the breakdown voltage ( ${V} _{\text {BR}}$ ) and reduced the degradation in dynamic ${R} _{ON}$ . With proper passivation techniques, these devices could be very promising as high-performance power switches for future power applications.

Comparative Analysis of Various Parameters of Tri-Gate MOSFET with High-K Spacer

In this paper, a comparative analysis of the Tri-gate MOSFET device structure with respect to Single Material Gate (SMG) Tri-gate MOSFET, Double Material Gate (DMG) Tri-gate MOSFET and Triple Material Gate (TMG) Tri-gate MOSFET with & without Hafnium dioxide as high-K dielectric material is employed using Silvaco TCAD Atlas Tool. It shows a compact model and better DC, AC performance for triple material gate structures and yields a high drive current of the device for TMG Tri-gate MOSFET with high-k dielectrics and shows a better electrical characteristics in comparison with other device structures.

Subthreshold Characteristic Analysis and Models for Tri-Gate SOI MOSFETs Using Substrate Bias Induced Effects

This paper proposes the substrate bias voltage dependent subthreshold models of channel potential, threshold voltage, current, drain induced barrier lowering, and subthreshold swing for tri-gate silicon-on-insulator (SOI) MOSFET s (TG- MOSFET s). The substrate induced surface potential effect has also been included in the derived models. A quasi-three-dimensional (3-D) approach has been used to derive the minimum of channel potential, which is later used to derive models of threshold voltage, current, drain induced barrier lowering, and swing. The analytical results of TG-SOI MOSFET have been compared with the simulation results obtained from the Visual TCAD, a 3-D device simulator from Cogenda Pvt. Ltd.

Vertical Tri-Gate Power MOSFETs in 4H-SiC

A new class of power MOSFET, the vertical tri-gate MOSFET, is described and analyzed. The structure can reduce the 4H-SiC MOS channel resistance by up to an order-of-magnitude, producing the same benefit as if the mobility were increased by the same factor. In this paper we outline the fabrication procedure and describe the unit processes unique to this structure.

The impact of heat loss paths on the electrothermal models of self-heating effects in nanoscale tri-gate SOI MOSFETs

The impact of heat loss paths on the electrothermal models of self-heating effects in nanoscale tri-gate SOI MOSFETs

A Method for Determining Trap Distributions of Specific Channel Surfaces in InGaAs Tri-Gate MOSFETs

We present a method for estimating the trap distributions on each of the surfaces in a multi-gate MOSFET. We perform I–V hysteresis measurements on InGaAs Tri-gate MOSFETs with various channel widths (25, 60, and 100 nm) from which top surface and side wall trap distributions are determined. We show that the total trap distribution of a device can be expressed as a linear combination of the top surface and side wall trap distributions. The results show that the minimum trap density of the top InGaAs (100) surface is smaller than that of the {110} side walls by almost an order of magnitude. Since the nanowire constituting the channel in these devices is selectively regrown, rather than etched out, the different trap distributions can be explained by the specific surface chemistries of two surfaces.

Junctionless tri-gate InGaAs MOSFETs

We demonstrate and characterize junctionless tri-gate InGaAs MOSFETs, fabricated using a simplified process with gate lengths down to Lg = 25 nm at a nanowire dimension of 7 × 16 nm2. These devices use a single 7-nm-thick In0.80Ga0.20As (ND = 1 × 1019 cm−3) layer as both channel and contacts. The devices show SSsat = 76 mV/dec, peak gm = 1.6 mS/µm and ION = 160 µA/µm (at IOFF = 100 nA/µm and VDD = 0.5 V), the latter which is the highest reported value for a junctionless FET. We also show that device performance is mainly limited by high parasitic access resistance due to the narrow and thin contact layer.

Underestimation of measured self‐heating in nanowires by using gate resistance technique

The channel temperature rise is demonstrated due to self-heating in narrow tri-gate fully depleted silicon-on-insulator devices becomes inaccurate when extracted using the gate resistance thermometry. Thermal resistance and channel temperature have been extracted by both gate resistance measurements and 3D TCAD electrothermal simulations for tri-gate wide and nanowire MOSFETs down to 12.5 nm fin width. A critical fin width around 500 nm the extracted channel temperature accessed by the gate resistance thermometry differs significantly from the actual channel temperature due to heat dissipation through the gate contacts is shown below, leading to significantly underestimated values.

Development of non-Fourier thermal attitude for three-dimensional and graphene-based MOS devices

In this paper, the intact subject of 3-D MOSFETs is studied. Three well-known 3-D MOSFET nano-devices, including a common three dimensional silicon MOSFET, the FinFET, and the Tri-Gate, are dealt. Firstly, by implying the three dimensional non-linear Dual-Phase-Lag method, the obtained results are verified with the existent data. Contemporaneously, the important parameter B=τt/τq, which is prerequisite for DPL modeling, is found for the 3-D silicon. The adjusted parameter B, is used to study the 3-D transistors with temperature-dependent thermal characteristics. It is found that taking into account such relevancy, makes the overall trends of distributions unmodified. Finally, the effect of contemplating the graphene sheet heat remover in a 3-D Tri-Gate MOSFET is investigated. Notably, the graphene makes the process of cooling the transistor get accelerated. It is obtained that 40ps after switching off the heat generation region, the value of the peak temperature of a 3-D Tri-Gate transistor along the center-line with a graphene heat remover, becomes 20% lower than that of a common 3-D Tri-Gate MOSFET. This finding shows that the Fourier calculations, overestimate the results.

III–V tri-gate quantum well MOSFET: Quantum ballistic simulation study for 10 nm technology and beyond

In this work, quantum ballistic simulation study of a III–V tri-gate MOSFET has been presented. At the same time, effects of device parameter variation on ballistic, subthreshold and short channel performance is observed and presented. The ballistic simulation result has also been used to observe the electrostatic performance and Capacitance–Voltage characteristics of the device. With constant urge to keep in pace with Moore’s law as well as aggressive scaling and device operation reaching near ballistic limit, a full quantum transport study at 10nm gate length is necessary. Our simulation reveals an increase in device drain current with increasing channel cross-section. However short channel performance and subthreshold performance get degraded with channel cross-section increment. Increasing device cross-section lowers threshold voltage of the device. The effect of gate oxide thickness on ballistic device performance is also observed. Increase in top gate oxide thickness affects device performance only upto a certain value. The thickness of the top gate oxide however shows no apparent effect on device threshold voltage. The ballistic simulation study has been further used to extract ballistic injection velocity of the carrier and ballistic carrier mobility in the channel. The effect of device dimension and gate oxide thickness on ballistic velocity and effective carrier mobility is also presented.

3D thermal conduction in a nanoscale Tri-Gate MOSFET based on single-phase-lag model

With the introduction of the new silicon on insulator (SOI)-Tri-Gate MOSFET technologies, it is very necessary to simulate the thermal performance in these nano devices. We have to notice that heat conduction given by Fourier's law ceases to be valid in nanostructures, due to the finite heat propagation speed in nanoscale regime. In this paper, we propose a thermal model given by the 3D single-phase-lag (SPL) model to predict the phonon transport in a 3D MOSFET and a Tri-Gate SOI-MOSFET. Considering the phonon-wall collisions, the SPL model is coupled with a new 3D second-order temperature-jump boundary condition. Using the finite element method we found that our proposed model is able to predict the thermal performance of a 10 nm 3D MOSFET and a 10 nm Tri-Gate SOI-MOSFET. The results reveal that the increase of the wall number leads to a decrease of the temperature field in the Tri-Gate structures. The results prove also that the channel width has an important role in the increasing of the temperature.

A New Subthreshold Current Model for Junctionless Trigate MOSFETs to Examine Interface-Trapped Charge Effects

On the basis of the effects of interface-trapped charges on the flat-band voltage, quasi-3-D scaling equation, and Pao-Sah’s integral, a novel subthreshold current model is presented for the junctionless trigate (JLTG) MOSFETs to examine interface-trapped charge effects (ITCEs). It indicates that a thin gate oxide can effectively reduce the subthreshold current degradation caused by the ITCEs. In contrast to the thin gate oxide, a thick silicon is required to alleviate the subthreshold current degradation caused by the ITCEs. For the short-channel behavior, the positive-/negative-trapped charges can enhance/alleviate short-channel effects (SCEs) for the device. As opposed to SCEs, the long-channel JLTG transistor suffers severe ITCEs than the short-channel device. Besides, the JL double-gate device with less gate coverage of the channel can reduce more subthreshold current degradation caused by the ITCEs than both the JLTG and JL quadruple-gate devices. Due to its computational efficiency, the model can be easily used to explore the hot-carrier-induced current behavior for the fully depleted JLTG MOSFETs for its memory cell application.

The Role of Geometry Parameters and Fin Aspect Ratio of Sub-20nm SOI-FinFET: An Analysis Towards Analog and RF Circuit Design

Nowadays FinFETs integrated into complex circuit applications can fulfill the demand of smartphones and tablets for better performance and make chips that can compute faster. This paper studies the impact of $H_{{\rm Fin}}$ and $W_{{\rm Fin}}$ variations on various performance matrices including static as well as dynamic figures of merit (FOMs). With the help of aspect ratio ( $W_{{\rm Fin}}/H_{{\rm Fin}}$ ), the device is branched into three parts, i.e., FinFET, Trigate, and Planar MOSFET. This unique report is a presentation of a detailed analysis about the impact of fin height ( $H_{{\rm Fin}}$ ) and width ( $W_{{\rm Fin}}$ ) on various performances including the dc as well as ac FOMs. The static or low-frequency performances like threshold voltage ( $V_{{\rm th}}$ ), on current ( $I_{{\rm on}}$ ), off current ( $I_{{\rm off}}$ ), power dissipation, transconductance ( $g_{{\rm m}}$ ), output conductance ( $g_{{\rm d}}$ ), transconductance generation factor ( $TGF = g_{{\rm m}}/I_{{\rm D}}$ ), early voltage ( $V_{{\rm EA}}$ ), gain ( $A_{{\rm V}}$ ), and dynamic or high-frequency performances as gate capacitance ( $C_{{\rm gg}}$ ), cutoff frequency ( $f_{{\rm T}}$ ), output resistance ( $R_{{\rm 0}}$ ), intrinsic delay are systematically presented with the variation of device geometry parameters. The results presented in this paper can be of great help to device engineers in designing 3-D devices as per their requirement.

III-V Tri-Gate Quantum-Well Mosfet for 10nm Technology and Beyond

With sub-10nm node technology approaching fast, counteracting short channel effects (SCEs), sub-threshold conduction, reducing transistor off-current and gate leakage current have become aspects of real concern. Integration of III-V semiconductors in multigate device architectures has become a topic of intense research and study for low power logic implementation [1]. Multigate device architectures like FinFETs, GAA FETs provide better control over channel carrier accumulation and improved short channel performance over planar structures. Recently, In0.53GA0.47As Quantum-Well (QW) Tri-Gate MOSFET with bi-layer high-k dielectrics of Al2O3/HfO2 has been reported with channel width and height scaled down to 30nm and 20nm respectively and gate length scaled down to 60nm [2]. In this work, we present a simulation study of inversion Capacitance-Voltage (C-V) and Threshold (VTH) characteristics of a III-V tri-gate device (Fig.1 inset) using self-consistent modeling. The device structure used for modeling in this study incorporates 2nm Al2O3 with In composition kept at 0.7 in the undoped InGaAs QW channel. The In0.52Al0.48As back barrier thickness is kept at 60nm. In this study TiN has been used as the gate metal. In all these studies, temperature is considered to be fixed at 300K. Finite Element Method (FEM) has been used to solve Schrodinger-Poisson equations in a coupled manner applying proper boundary conditions, using COMSOL Multiphysics and MATLAB, taking into account wave function penetration and other quantum mechanical effects. 2D Schrodinger equation is solved using effective mass approximation and open boundary condition to determine electron wave functions and eigen states in the quantum well. Using carrier wave functions in the tri-gate channel, inversion carrier concentration is determined by applying 1D density of states and Fermi-Dirac distribution function. The effect of fixed oxide charges, interface trap charges and oxide border trap charges is not taken into account. The developed simulator is also benchmarked with the simulation results obtained for a III-V GAA nanowire transistor [3]. A quantum definition of threshold voltage for multigate FETs is available in literature [4]. According to this definition, the threshold voltage can be presented as a combination of classical and quantum terms. Here, peak electron concentration npeak(x,y) and average electron concentration navg are used to define threshold voltage of the device. At threshold point, the profile of npeak(x,y)/navg would show a change in slope which results from shift in carrier accumulation as device operation moves from subthreshold to inversion mode [4]. In this study, same definition of threshold voltage has been used. The simulation reveals strong carrier accumulation at the corners of the oxide/semiconductor interface which is expected for multigate device structures (Fig. 1). The simulation also reveals strong subband quantization in the QW channel (Fig. 2). Occupied subbands below the Fermi level contribute to the carrier concentration. As the device dimension is shrunk, volume inversion effect becomes more and more significant and carriers begin to accumulate at the middle portion of the tri-gate channel. This phenomenon leads to an increase in carrier concentration in the middle portion of the QW fin as channel dimension is scaled (Fig. 3). This phenomenon shifts channel formation towards the middle portion of the tri-gate QW fin. Simulation also reveals higher inversion capacitance at lower In composition in the channel which may be attributed to higher density of states effective mass at lower In composition (Fig. 4). Although variation of top gate oxide thickness reveals effect on inversion capacitance, the threshold voltage remains mostly unchanged with top gate oxide thickness. Study of variable channel dimension while keeping WFin=HFin reveals lower carrier accumulation in the device cross section per unit channel length which may lead to lower inversion capacitance with lower channel dimension (Fig. 5). Lowering channel dimension results in stronger quantum confinement and subband splitting which eventually leads to an increase in threshold voltage (Fig. 6). Lowered In composition in the channel also increases threshold voltage of the device (Fig. 6). In this work, a simulation study of a III-V tri-gate quantum well device for 10nm technology and beyond is presented. The outcome of this work would be useful in the implementation of III-V multigate device structures for high speed and low power logic applications.

Low-frequency noise reduction in vertical MOSFETs having tunable threshold voltage fabricated with 60 nm CMOS technology on 300 mm wafer process

In this paper, DC and low-frequency noise (LFN) characteristics have been investigated with actual measurement data in both n- and p-type vertical MOSFETs (V-MOSFETs) for the first time. The V-MOSFETs which was fabricated on 300 mm bulk silicon wafer process have realized excellent DC performance and a significant reduction of flicker (1/f) noise. The measurement results show that the fabricated V-MOSFETs with 60 nm silicon pillar and 100 nm gate length achieve excellent steep sub-threshold swing (69 mV/decade for n-type and 66 mV/decade for p-type), good on-current (281 µA/µm for n-type 149 µA/µm for p-type), low off-leakage current (28.1 pA/µm for n-type and 79.6 pA/µm for p-type), and excellent on–off ratio (1 × 107 for n-type and 2 × 106 for p-type). In addition, it is demonstrated that our fabricated V-MOSFETs can control the threshold voltage (Vth) by changing the channel doping condition, which is the useful and low-cost technique as it has been widely used in the conventional bulk planar MOSFET. This result indicates that V-MOSFETs can control Vth more finely and flexibly by the combined the use of the doping technique with other techniques such as work function engineering of metal-gate. Moreover, it is also shown that V-MOSFETs can suppress 1/f noise ( of 10−13–10−11 µm2/Hz for n-type and 10−12–10−10 µm2/Hz for p-type) to one or two order lower level than previously reported nanowire type MOSFET, FinFET, Tri-Gate, and planar MOSFETs. The results have also proved that both DC and 1/f noise performances are independent from the bias voltage which is applied to substrate or well layer. Therefore, it is verified that V-MOSFETs can eliminate the effects from substrate or well layer, which always adversely affects the circuit performances due to this serial connection.