Tri-gate Junctionless Transistors Research Articles

Tri-gate junctionless transistors with electrostatically highly doped channel

Multiple-gated junctionless transistors (JLTs) with an extremely simple structure and bulk-conduction-based operation could overcome fundamental problems with respect to short-channel effects for sub-3-nm technology nodes. In this paper, the performance of a tri-gate JLT with an electrostatically highly doped channel is demonstrated through numerical simulation. Unique characteristics previously reported in fabricated JLTs were exhibited by the tri-gate transistors with an additional bottom-gate bias (Vgb = 50 V), which induced an effectively highly doped state of the channel. The results of this study show the feasibility of producing impurity scattering-free JLTs for next-generation technology nodes.

Channel-Width-Dependent Mobility Degradation in Bulk Conduction Regime of Tri-Gate Junctionless Transistors

Junctionless transistors (JLTs) have promising strengths such as extremely simple structures without p-n junctions, better reliability, and low flicker noise, for overcoming scaling challenges for advanced sub-5-nm nodes. In this article, channel-width-dependent operation in the partially depleted regime of tri-gate JLTs was investigated in comparison to conduction in conventional inversion-mode (IM) transistors. A large difference in transconductance (gₘ) against gate-to-channel capacitance (C <formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex>$_{gc}$</tex> </formula> ) and the reduced amplitude of the first peak on dgₘ/dV <formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex>$_{g}$</tex> </formula> were identified under the partially depleted regime in JLTs, due to a severe transverse E-field near-threshold voltage (V <formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex>$_{th}$</tex> </formula> ). However, the impact of E-field was weakened as decreasing channel width of JLTs. These works provide key information for a better understanding of the channel-width-dependent performance of JLTs and for implementing practical applications with them.

Channel geometry-dependent threshold voltage and transconductance degradation in gate-all-around nanosheet junctionless transistors

The gate-all-around (GAA) nanosheet (NS) junctionless transistor (JLT) is an attractive candidate for advanced technology nodes in CMOS scaling. Here, the channel width-dependent transconductance (gm) degradation and threshold voltage (Vth) shift of GAA NS JLTs were investigated via numerical simulation. Compared to bulk neutral channels, a pronounced surface accumulation channel limited the overall electrical characteristics of GAA NS JLTs at narrow widths. Additionally, the variation in Vth of GAA NS JLTs was much smaller than that in tri-gate JLTs. Quantum mechanical effects in GAA NS JLTs with a very narrow width were also investigated.

Self-heating and Negative Differential Conductance Improvement by Substrate Bias Voltage in Tri-gate Junctionless Transistor

Self-heating effects (SHE) in silicon-on-insulator (SOI) based tri-gate junctionless field effect transistor (TG-JLFET) due to low thermal conductivity of buried oxide (SiO2) is studied in this paper. Self-heating results in degradation of drain current due to reduced mobility and also negative differential conductance (NDC) is seen in saturation region. This paper shows that substrate bias voltage can dynamically reduce self-heating and NDC in TG-JLFETs. The analysis is carried out by three-dimensional TCAD simulation using Sentaurus device simulator.

Channel width dependent subthreshold operation of tri-gate junctionless transistors

Junctionless transistors (JLTs) are one of attractive candidates for further scaling down thanks to their promising advantages based on a structural simplicity without PN junctions, and their physical operation is quite different from traditional inversion-mode (IM) transistors. In this paper, we investigated the subthreshold operation of tri-gate JLTs with various effective width (Weff) and compared to that of IM transistors. The on current to off current ratio (Ion/Ioff) and subthreshold swing (SS) of JLTs were varied dramatically as changing Weff. In addition, a better immunity against short channel effects (SCEs) of JLTs was proven. Physical operation mechanism on the subthreshold regime was also discussed in detail with considering distribution of mobile charge carriers, maximum depletion width, full-depletion mode, bulk neutral and surface accumulation conduction.

Accurate determination of low-field mobility in tri-gate junctionless transistors

The simple device structure of junctionless transistors (JLTs), which lack PN junctions and involve bulk-conduction-based operation, is an attractive component for the future fulfilment of Moore’s law. However, the unique bulk conduction mechanism of JLTs introduces inaccuracies in low-field mobility (μ0) extracted from conventional Y-function method. The top channel width-dependent μ0 error of tri-gate JLTs was investigated using numerical simulation and analytical modeling. This work provides important information for an accurate determination of μ0 in tri-gate JLTs.

Thermal Noise Models for Trigate Junctionless Transistors Including Substrate Bias Effects

Thermal noise power spectral density (PSD) models for trigate junctionless field-effect transistors (TG-JLFETs) incorporating substrate bias effects are developed in this article. The PSDs of drain current thermal noise, induced gate noise, and cross correlation between the two noises are derived for TG-JLFET using the modified Klaassen and Prins (KP) equation. An all-region drain current model of TG-JLFET is used to obtain the aforementioned thermal noises. Thermal noise PSD in TG-JLFET depends on channel conductance, and substrate bias voltage significantly modulates the channel conductance, and thus, the substantial impact of substrate bias can be observed on thermal noise of TG-JLFET. Model results are validated with the simulation results obtained using a 3-D technology computer-aided design (TCAD)-based device simulator from Synopsys.

Static and Quasi-Static Drain Current Modeling of Tri-Gate Junctionless Transistor With Substrate Bias-Induced Effects

In this paper, a surface potential-based drain current model is developed to explore the static and quasi-static performance of substrate-biased tri-gate junctionless field-effect-transistors (TGJLFETs). The effects of substrate bias voltage on surface potential, charge density, and drain current are analyzed. The 2-D Poisson’s equation is solved to obtain front and back surface potentials incorporating the effect of substrate bias voltage for a long-channel TGJLFET. The front and back surface potentials are subsequently utilized to obtain total conduction charge density and drain current. Further, short-channel and quantum mechanical corrections are incorporated in the model to use it for scaled devices. Moreover, the terminal charges calculated using Ward–Dutton’s charge partitioning scheme are utilized to model the transcapacitances and quasi-static drain current for TGJLFET. Further, an equivalent large-signal transient model of the device is implemented in SPICE using Verilog-A, and the transient behavior of inverter and ring oscillator circuits are simulated and studied. The models are validated using a 3-D Visual TCAD device simulator from Cogenda Pvt. Ltd.

Relevance of Device Cross Section to Overcome Boltzmann Switching Limit in 3-D Junctionless Transistor

In this paper, the requirements of device cross section and aspect ratio (AR) are examined to facilitate steep switching in heavily doped 3-D multiple gate junctionless (JL) transistors. It is shown through well-calibrated simulations and physical insights that the sharp OFF-to- ON switching action is predominantly governed by the area of cross section ( ${A} _{\textsf {cross}}$ ) instead of the gate length. A 3-D JL architecture preferably oriented toward a planar topology, i.e., with wider fin and low AR, is conducive for steep switching as a greater bulk area is available for impact ionization. On the contrary, narrow vertical architectures with AR > 1 suppress ${A} _{\textsf {cross}}$ in the bulk and are less likely to support the steep current transition. Steep switching specific scaling methodology is showcased to attain a sharp increase in drain current with a sub-60 mV/decade swing in a tri-gate JL transistor along with an associated negative value of total gate capacitance.

A Simple Method for Estimation of Silicon Film Thickness in Tri-Gate Junctionless Transistors

Junctionless transistors (JLTs) without PN-junctions near the source/drain are promising candidates for further development of CMOS technology. The Si thickness of tri-gate JLTs is crucial to understand their unique electrical properties related to bulk neutral and surface accumulation conduction. A simple method based on a unique operation mechanism is suggested for extraction of $\text{t}_{\mathrm {si}}$ from measurements on tri-gate JLTs. The method was successfully applied to fabricated tri-gate JLTs and the extracted $\text{t}_{\mathrm {si}}$ values were comparable with those of transmission electron microscopy. Furthermore, the validity of the method was confirmed by 2-D numerical simulation.

Subthreshold Modeling of Tri-Gate Junctionless Transistors With Variable Channel Edges and Substrate Bias Effects

In this paper, subthreshold channel potential, current, swing, threshold voltage, and drain-induced barrier lowering models of short-channel tri-gate junctionless field-effect transistors are presented. The models incorporate the effects of both substrate-induced surface potential and variable edges of channel. The quasi-3-D approach is used for the modeling of minimum of channel potential that is subsequently used in the drift–diffusion equation to obtain the current expression in subthreshold regime. Threshold voltage and subthreshold swing models are also based on the minimum of channel potential. The analytical results are compared with the simulation data obtained using 3-D visual TCAD device simulator from Cogenda Pvt., Ltd.

Analog/RF performance of source-side only dual-k sidewall spacer trigate junctionless transistor with parametric variations

In this paper, analog/RF performance of source side only dual-k spacer (Dual-kS) trigate junctionless transistor (JLT) is investigated with respect to the parametric variations. It is observed that the Dual-kS JLT improves analog/RF figure of merits (FOMs) and shows its lower dependence to the parametric variations compared with the conventional (low-k spacer) JLT. This study reveals that the design of Dual-kS JLT with lower aspect ratio (1–3) improves the analog FOMs with moderate frequency of operations at fin-width of 10 nm with gate length being 20 nm. Moreover, the frequency of operation can be increased further by increasing the aspect ratio (4–6) without sacrificing the analog FOMs such as transconductance (gm), output conductance (gds) and intrinsic voltage gain (AV0). It is also reported that gds of Dual-kS JLT is least sensitive to the variation in fin-width, doping concentration and oxide thickness, which proves the potential of Dual-kS device to act as a constant current source. Moreover, Dual-kS device is found to be robust against the variation in doping concentration and oxide thickness, which further improves the merit of Dual-kS JLT for low-voltage/low-power analog/RF applications.

Investigation of trigate JLT with dual-k sidewall spacers for enhanced analog/RF FOMs

This paper shows the potential benefits of using the trigate junctionless transistor (JLT) with dual-k sidewall spacers to enhance analog/radio-frequency (RF) performance at 20-nm gate length. Simulation study shows that the source-side-only dual-k spacer (dual-kS) JLT can improve all analog/RF figures of merit (FOMs) compared with the conventional JLT structure. The dual-kS JLT shows improvement in intrinsic voltage gain ($$A_{V0}$$AV0) by $$\sim $$~44.58 %, unity-gain cutoff frequency ($$f_\mathrm{T}$$fT) by $$\sim $$~7.67 %, and maximum oscillation frequency ($$f_\mathrm{MAX}$$fMAX) by $$\sim $$~6.4 % at drain current $$(I_\mathrm{ds}) = 10\,\upmu \hbox {A}/\upmu \hbox {m}$$(Ids)=10μA/μm compared with the conventional JLT structure. To justify the improvement in all analog/RF FOMs, it is also found that the dual-kS structure shows high electron velocity near the source region because of the presence of an additional electric field peak near the source region, resulting in increased electron transport efficiency and hence improved transconductance ($$g_\mathrm{m}$$gm). Furthermore, the dual-kS JLT shows a reduction in the electric field value near the drain end, thereby improving short-channel effects.

Back biasing effects in tri-gate junctionless transistors

The back bias effect on tri-gate junctionless transistors (JLTs) has been investigated using experimental results and 2-D numerical simulations, compared to inversion-mode (IM) transistors. Results show that JLT devices are more sensitive to back biasing due to the bulk conduction. It is also shown that the effective mobility of JLT is significantly enhanced below flat band voltage by back bias. However, in extremely narrow JLTs, the back bias effect is suppressed by reduced portion of bulk conduction and strong sidewall gate controls. 2-D numerical charge simulation well supports experimental results by reconstructing the trend of back bias effects.

A new method for the extraction of flat-band voltage and doping concentration in Tri-gate Junctionless Transistors

A new method for the extraction of flat-band voltage (Vfb) and channel doping concentration (Nd) in Tri-gate Junctionless Transistors (JLTs) is presented. The new method, based on the relationship between the top-effective width (Wtop_eff) in accumulation and the effective width (Weff′) in partial depletion, enables the extraction of Vfb and Nd of JLT devices (here as ≈0.61V and ≈6.4×1018cm−3, respectively). The validity of the new method is also proved by 2D numerical simulations. Furthermore, it is emphasized that the sidewall accumulation current (Id_side) behavior of Tri-gate JLT devices is found to decrease dramatically near Vfb, allowing an estimation of the Vfb position of JLT devices.

Effects of channel width variation on electrical characteristics of tri-gate Junctionless transistors

The electrical behavior of tri-gate Junctionless transistors (JLTs) depending on top-effective width (Wtop_eff) was investigated, experimentally. As decreasing Wtop_eff, the amount of bulk neutral channel is relatively getting smaller than that of surface accumulation channel, whereas the channel sidewall gate effect is reinforced. These cause the shrinkage of the shoulder shape on the gate-to-channel capacitance characteristics (Cgc–Vg), resulting in a noticeable change in the effective mobility (μeff) behavior from that in wide JLT devices, an increase of the threshold voltage (Vth), while the flat-band voltage (Vfb) does not change. 2D numerical simulation results, well consistent to the experimental results, confirm the significant sidewall gate effect in the tri-gate JLT devices with a narrow structure.