Abstract
The electrical behavior of tri-gate Junctionless transistors (JLTs) depending on top-effective width (Wtop_eff) was investigated, experimentally. As decreasing Wtop_eff, the amount of bulk neutral channel is relatively getting smaller than that of surface accumulation channel, whereas the channel sidewall gate effect is reinforced. These cause the shrinkage of the shoulder shape on the gate-to-channel capacitance characteristics (Cgc–Vg), resulting in a noticeable change in the effective mobility (μeff) behavior from that in wide JLT devices, an increase of the threshold voltage (Vth), while the flat-band voltage (Vfb) does not change. 2D numerical simulation results, well consistent to the experimental results, confirm the significant sidewall gate effect in the tri-gate JLT devices with a narrow structure.
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