Trench Oxide Research Articles

The L28 STI CMP Dummy Pattern Study on Topography for Advanced Fixed Abrasive and High Selective Slurry

The STI CMP performance was major determined by the uniformity of STI step height which was characterized by the ranges of within-die (WID) and within-wafer (WIW) thickness for both silicon nitride and trench oxide surface of isolation area. Currently, for 28nm generation, two advanced approaches for STI CMP were high selective slurry (HSS) and fixed abrasive (FA) CMP. For these two approaches, the design and layout of dummy were important to overcome the effect of various pattern densities and feature sizes. Therefore this research focused on the effect of dummy type for HSS and FA CMP. The result shows HSS CMP is the most robust process in STI CMP. The nitride thickness after HSS CMP shows good uniformity, 2~3 %, and is slightly affected by dummy type and PD of test key comparing with FA CMP.

Physical Evidence Supporting the Electrical Signature of SEGR on Thin Vertical Oxides

Analysis techniques have been done to provide the physical evidence that the electrical signature observed from a single event gate rupture (SEGR) event on a deep trench oxide capacitor from 90nm bulk complementary metal oxide semiconductor (CMOS) technology, used for the reduction of single event upsets (SEU), does identify that dielectric breakdown has occurred. SEGR damaged trench oxides were identified via a voltage contrast technique using a focused ion beam (FIB). The FIB was used to delayered and expose the deep trenches. A wet chemical etch was used to identify the location of SEGR leakage path. The oxide rupture location was observed at the top of the deep trench capacitor.

Improvement of AC characteristics of FITMOS

The AC characteristics of a FITMOS (Floating Island and Thick bottom oxide trench gate MOSfet) with passive hole gate structures are investigated under limiting conditions of high voltage, high temperature and long trench length. The origin of time delay in the switching operation is discussed based on the experimental results and new device structures applicable to the high voltage and high temperature operation are proposed. No additional switching delay is observed in the new structure. Furthermore, degradation in the drain-source breakdown characteristic, as well as the characteristics for the unclamped inductive switch test, is observed.

Single transverse mode control of VCSEL by photonic crystal and trench patterning

Single transverse mode control is achieved for multimode GaAs-based VCSEL by utilizing photonic crystal design and etched trench structure. Theoretical analysis is initially performed for photonic crystal design with various lattice constants and air holes diameter. The fabricated photonic crystal VCSEL with etched trench structure exhibits single mode output power of 0.7 mW, threshold current of 3.5 mA, slope efficiency of 0.10 W/A, and continuous single mode output spectrum throughout a wide operating current range. Comparison of typical oxide VCSEL, trench oxide VCSEL, and photonic crystal oxide VCSEL employing trench structure is presented. By combining photonic crystal and trench structure, single transverse mode operation of photonic crystal VCSEL can be much more strictly controlled.

Effects of trench oxide and field plates on the breakdown voltage of SOI LDMOSFET

To improve the breakdown voltage, we propose a SOI-based LDMOSFET with a trench structure in the drift region. Due to the trench oxide and underneath boron implanted layer, the surface electric field in the drift region effectively reduced. These effects resulted in the increment of breakdown voltage for the trenched LDMOS more than 100 V compared with the conventional device. However, the specific on-resistance, which has a trade-off relationship, is slightly increased. In addition to the trench oxide on the device performance, we also investigated the influence of n− drift to n+ drain junction spacing on the off-state breakdown voltage. The measured breakdown voltages were varied more than 50 V with different n− to n+ design spaces and achieved a maximum value at L DA = 2.0 μm. Moreover, the influence of field plate on the breakdown voltage of trench LDMOSFET was investigated. It is found that the optimum drain field plate over the field oxide is 8 μm.

Fabrication of Low-Defectivity, Compressively Strained Ge on Si0.2Ge0.8 Structures Using Aspect Ratio Trapping

Low-defectivity, compressively strained Ge on was fabricated in oxide trenches using the aspect ratio trapping technique. This was accomplished through the use of pre-epi bakes optimized to remove interfacial impurities which can lead to defective epi layers. Pre-epi bake over the optimum temperature caused the release of stored elastic strain energy in the regions leading to undesirable undulations of the layers. Using the optimum prebake at , thick, compressively strained Ge was grown. It had 1 and 0.45% elastic strain along and perpendicular to the trench direction, respectively, which is well-suited for strained Ge channels in future complementary-metal-oxide semiconductor devices.

Low-Defect-Density Ge Epitaxy on Si(001) Using Aspect Ratio Trapping and Epitaxial Lateral Overgrowth

Low-defect-density Ge epitaxy was fabricated using aspect ratio trapping combined with epitaxial lateral overgrowth techniques. Dislocations from the Ge/Si interface were trapped inside oxide trenches, and then Ge was laterally grown to form 20 μm wide, 6 mm long strips. Chemical mechanical polishing of Ge was used to planarize the faceted strips. Uncoalesced Ge strips showed a defect density as low as 1.6 X 10 6 cm -2 from plan-view transmission electron microscopy, while coalesced Ge had higher defect density. This approach shows great promise for the integration of low-defect-density Ge and III-V materials on Si.

New High-Voltage ($>$ 1200 V) MOSFET With the Charge Trenches on Partial SOI

A novel silicon-on-insulator (SOI) high-voltage MOSFET structure and its breakdown mechanism are presented in this paper. The structure is characterized by oxide trenches on the top interface of the buried oxide layer on partial SOI (TPSOI). Inversion charges located in the trenches enhance the electric field of the buried layer in the high-voltage blocking state, and a silicon window makes the depletion region spread into the substrate. Both of them modulate the electric field in the drift region; therefore, the breakdown voltage (BV) for a TPSOI LDMOS is greatly enhanced. Moreover, the Si window alleviates the self-heating effect. The influences of the structure parameters on device characteristics are analyzed for the proposed device structure. The TPSOI LDMOS with BV > 1200 V and the buried-layer electric field of EI > 700 V/ mum is obtained by the simulation on a 2-mum-thick SOI layer over 2-mum-thick buried oxide layer, and its maximal temperature reduces by 19 and 8.7 K in comparison with the conventional SOI and partial SOI devices.

Imaging Mechanical Vibrations in Suspended Graphene Sheets

We carried out measurements on nanoelectromechanical systems based on multilayer graphene sheets suspended over trenches in silicon oxide. The motion of the suspended sheets was electrostatically driven at resonance using applied radio frequency voltages. The mechanical vibrations were detected using a novel form of scanning probe microscopy, which allowed identification and spatial imaging of the shape of the mechanical eigenmodes. In as many as half the resonators measured, we observed a new class of exotic nanoscale vibration eigenmodes not predicted by the elastic beam theory, where the amplitude of vibration is maximum at the free edges. By modeling the suspended sheets with the finite element method, these edge eigenmodes are shown to be the result of nonuniform stress with remarkably large magnitudes (up to 1.5 GPa). This nonuniform stress, which arises from the way graphene is prepared by pressing or rubbing bulk graphite against another surface, should be taken into account in future studies on electronic and mechanical properties of graphene.

3D Monte Carlo simulation of transport in electro‐statically confined silicon nanochannels

AbstractThis study investigates transport and electrostatic behavior of quasi 1D nanowires adopting a relatively simple planar fabrication technique. The confined conduction channel is created by etching an oxide trench, realizing a T‐gate structure. Since multiple channels are normally needed to realize sufficient current drive in practical applications, the behavior of single and coupled adjacent silicon nanowires is characterized using a 3D quantum corrected Monte Carlo approach. Results indicate that a single T‐gate structure provides over 27% increase in current drive compared to conventional MOSFET at a drain voltage of 1V. In addition, design consideration and recommendation is presented. Cross section of a T‐gate MOSFET. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Electromechanical Resonators from Graphene Sheets

Nanoelectromechanical systems were fabricated from single- and multilayer graphene sheets by mechanically exfoliating thin sheets from graphite over trenches in silicon oxide. Vibrations with fundamental resonant frequencies in the megahertz range are actuated either optically or electrically and detected optically by interferometry. We demonstrate room-temperature charge sensitivities down to 8 x 10(-4) electrons per root hertz. The thinnest resonator consists of a single suspended layer of atoms and represents the ultimate limit of two-dimensional nanoelectromechanical systems.

탄소나노튜브 팁의 집속이온빔에 의한 개선 및 성능 평가

This paper presents development of carbon nanotube (CNT) tip modified by focused ion beam (FIB) and experimental results in non-contact mode of atomic force microscopy (AFM) using fabricated tip. We used an electric field which causes dielectrophoresis, to align and deposit CNTs on a conventional silicon tip. The morphology of the fabricated CNT tip was then modified into a desired shape using focused ion beam. We measured anodic aluminum oxide sample and trench structure to estimate the performance of FIB-modified tip and compared with those of conventional Si tip. We demonstrate that FIB modified tip in non contact mode had superior characteristics than conventional tip in the respects of wear, image resolution and sidewall measurement.

A Nanodamascene Process to be used as a Building Block for Nanodevices

ABSTRACTWe report a single-electron transistor concept and its related process enabling the fabrication of ultrasmall junction capacitance. The method utilizes a nanodamascene approach where trenches in silicon oxide are covered with a filling material and planarized with chemical mechanical polishing. Single-electron transistors fabricated with this approach were characterized up to 433 K and demonstrated that the nanodamascene process has high resolution, is relatively simple and is highly scalable.

트렌치 산화막을 갖는 정전유도트랜지스터의 전기적 특성에 관한 연구

In this paper, two types of vertical SIT(Static Induction Transistor) structures are proposed to improve their electrical characteristics including the blocking voltage. Besides, the two dimensional numerical simulations were carried out using ISE-TCAD to verify the validity of the device and examine the electrical characteristics. First, a trench gate region oxide power SIT device is proposed to improve forward blocking characteristics. Second, a trench gate-source region power SIT device is proposed to obtain more higher forward blocking voltage and forward blocking characteristics at the same size. The two proposed devices have superior electrical characteristics when compared to conventional device. In the proposed trench gate oxide power SIT, the forward blocking voltage is considerably improved by using the vertical trench oxide and the forward blocking voltage is 1.5 times better than that of the conventional vertical power SIT. In the proposed trench gate-source oxide power SIT, it has considerable improvement in forward blocking characteristics which shows 1500V forward blocking voltage at -10V of the gate voltage. Consequently, the proposed trench oxide power SIT has the superior stability and electrical characteristics than the conventional power SIT.

Near-infrared diode laser hydrogen fluoride monitor for dielectric etch

A hydrogen fluoride (HF) monitor, using a tunable diode laser, is designed and used to detect the etch endpoints for dielectric film etching in a commercial plasma reactor. The reactor plasma contains HF, a reaction product of feedstock gas CF4 and the hydrogen-containing films (photoresist, SiOCH) on the substrate. A near-infrared diode laser is used to scan the P(3) transition in the first overtone of HF near 1.31μm to monitor changes in the level of HF concentration in the plasma. Using 200ms averaging and a signal modulation technique, we estimate a minimum detectable HF absorbance of 6×10−5 in the etch plasma, corresponding to an HF partial pressure of 0.03mTorr. The sensor could indicate, in situ, the SiOCH over tetraethoxysilane oxide (TEOS) trench endpoint, which was not readily discerned by optical emission. These measurements demonstrate the feasibility of a real-time diode laser-based sensor for etch endpoint monitoring and a potential for process control.

New SOI lateral power devices with trench oxide

We describe new SOI lateral power devices which have a trench oxide to improve the device performance. High-voltage super-junction (SJ) SOI-LDMOSFETs have a trench oxide in the drift region. It allows to reduce the drift length without degrading the breakdown voltage. With the proposed device structure a reduction of the on-resistance of the n-drift layer can be achieved. The breakdown voltage and the specific on-resistance of the suggested devices as a function of the trench oxide depth, the p-column width, and the doping are studied. Shorted-anode lateral insulated-gate bipolar transistors (SA-LIGBTs) on SOI have a trench oxide at the drain/anode region. It suppresses effectively the snap-back voltage inherent in conventional SA-LIGBTs without increasing the anode length of the device. Using the two-dimensional numerical simulator Minimos-NT, we confirm that the drift length of the proposed SJ SOI-LDMOSFETs is reduced to 65% compared to conventional devices, and a weak negative differential resistance region is observed with the proposed SOI SA-LIGBT.

스마트 파워 IC를 위한 트렌치 파워 MOSFET의 전기적 특성에 관한 연구

In this paper, a new small size Lateral Trench Electrode Power MOSFET is proposed. This new structure, called "LTEMOSFET"(Lateral Trench Electrode Power MOSFET), is based on the conventional MOSFET. The entire electrode of LTEMOSFET is placed in trench oxide. The forward blocking voltage of the proposed LTEMOSFET is improved by 1.6 times with that of the conventional MOSFET. The forward blocking voltage of LTEMOSFET is 250V. At the same size, a increase of the forward blocking voltage of about 1.6 times relative to the conventional MOSFET is observed by using TMA-MEDICI which is used for analyzing device characteristics. Because the electrodes of the proposed device are formed in trench oxide, the electric field in the device are crowded to trench oxide. We observed that the characteristics of the proposed device was improved by using TMA-MEDICI and that the fabrication of the proposed device is possible by using TMA-TSUPREM4.

Low Resistivity p[sup +] Polycrystalline Silicon Deposition at Low Temperatures with SiH[sub 4]/BCl[sub 3

The deposition of p + polycrystalline silicon films on SiO 2 substrates by SiH 4 /BCl 3 gases has been characterized. Films were deposited at temperatures as low as 460°C with an as-deposited resistivity of 3560 ′ 130 μΩ cm with good step coverage in oxide trenches. The extracted activation energy for silicon deposition was 0.6 eV for temperatures between 490 and 580°C and boron concentration of 2.0 ′ 0.4 X 10 2 1 /cm 3 , compared with 0.2 eV for p + silicon deposition by SiH 4 /B 2 H 6 for similar conditions. Silicon films deposited by SiH 4 /BCl 3 are polycrystalline with low resistivities as-deposited at 460°C, whereas films deposited by SiH 4 /B 2 H 6 are amorphous at deposition temperatures <520°C.

The Effect of Oxide Trenches on Defect Formation and Evolution in Ion-Implanted Silicon

ABSTRACTPattern induced defects during advanced CMOS processing can lead to lower quality devices with high leakage currents. Within this study, the effects of oxide trenches on implant related defect formation and evolution in silicon patterned wafers is examined. Oxide filled trenches approximately 4000Å deep were patterned into 300 mm &lt;100&gt; silicon wafers. Patterning was followed by ion implantation of Si+ at energies ranging from 10 to 80 keV. Samples were amorphized with doses of 1×1015 atoms/cm2, 5×1015 atoms/cm2, and 1×1016 atoms/cm2. Two independent repeating structures were studied. The first structure is comprised of silicon oxide filled trench lines, 3.7μm wide spaced 12.5μm apart, while the second structure contains silicon squares, 0.6μm on a side, surrounded by a silicon oxide filled trench. Cross- sectional and planar view transmission electron microscopy (TEM) samples were used to examine the defect morphology after annealing at temperatures ranging from 700°C to 950°C and at times between 1 second and 1 minute. Following complete regrowth, an array of defects was observed to form near the surface at the silicon/silicon oxide interface. These trench edge defects appeared to nucleate at the amorphous-crystalline interface for all energies and doses studied. Upon a spike anneal at 700°C, it was observed that regrowth of the amorphous layer had completed except in the region near the trench edge. Thus, it is believed that this defect results from the pinning of the amorphous-crystalline interface along the trench edge during solid phase epitaxial regrowth (SPER).

Directional effects on bound quantum states for trench oxide quantum wires on (1 0 0)-silicon

We examine the influence of channel axis orientation on bound electron states for trench oxide quantum wires built on (1 0 0)-silicon surfaces. We describe these structures by solving the coupled system of Schrödinger’s and Poisson’s equation selfconsistently using a realistic mass tensor for all six conductions band valleys. We find that for the structure examined aligning the channel axis with a (1 0 0)-direction has only a small influence on the spectrum of bound electron states and practically none on total channel occupation.