Trench Oxide Research Articles

A high voltage silicon-on-insulator lateral insulated gate bipolar transistor with a reduced cell-pitch

A high voltage (> 600 V) integrable silicon-on-insulator (SOI) trench-type lateral insulated gate bipolar transistor (LIGBT) with a reduced cell-pitch is proposed. The LIGBT features multiple trenches (MTs): two oxide trenches in the drift region and a trench gate extended to the buried oxide (BOX). Firstly, the oxide trenches enhance electric field strength because of the lower permittivity of oxide than that of Si. Secondly, oxide trenches bring in multi-directional depletion, leading to a reshaped electric field distribution and an enhanced reduced-surface electric-field (RESURF) effect. Both increase the breakdown voltage (BV). Thirdly, oxide trenches fold the drift region around the oxide trenches, leading to a reduced cell-pitch. Finally, the oxide trenches enhance the conductivity modulation, resulting in a high electron/hole concentration in the drift region as well as a low forward voltage drop (Von). The oxide trenches cause a low anode—cathode capacitance, which increases the switching speed and reduces the turn-off energy loss (Eoff). The MT SOI LIGBT exhibits a BV of 603 V at a small cell-pitch of 24 μm, a Von of 1.03 V at 100 A/cm−2, a turn-off time of 250 ns and Eoff of 4.1×10−3 mJ. The trench gate extended to BOX synchronously acts as dielectric isolation between high voltage LIGBT and low voltage circuits, simplifying the fabrication processes.

Deep oxide trench termination structure for super-junction MOSFET

Deep oxide trench isolation with a p-type pillar guard is suggested as the termination structure for a high voltage super-junction (SJ) MOSFET device. With an additional p-type pillar guard, such a structure can result in a trapezoidal field profile in depth along the oxide trench sidewall and the device has improved breakdown voltage limited by an intrinsic super-junction structure.

Study of radiation-induced leakage current between adjacent devices in a CMOS integrated circuit

Radiation-induced inter-device leakage is studied using an analytical model and TCAD simulation. There were some different opinions in understanding the process of defect build-up in trench oxide and parasitic leakage path turning on from earlier studies. To reanalyze this problem and make it beyond argument, every possible variable is considered using theoretical analysis, not just the change of electric field or oxide thickness independently. Among all possible inter-device leakage paths, parasitic structures with N-well as both drain and source are comparatively more sensitive to the total dose effect when a voltage discrepancy exists between the drain and source region. Since N-well regions are commonly connected to the same power supply, these kinds of structures will not be a problem in a real CMOS integrated circuit. Generally speaking, conduction paths of inter-device leakage existing in a real integrated circuit and under real electrical circumstances are not very sensitive to the total ionizing dose effect.

Analytical modelling of inverse narrow width effect for narrow channel STI MOSFETs

This paper presents an analytical physics-based model for the width dependence of threshold voltage of nano-scale MOSFETs considering the combined effect of gate-fringing and dopant redistribution. Shallow trench isolated MOSFETs have been considered in the 90 nm and 65 nm technology node. An analytical expression for the trench oxide parasitic capacitance is derived by taking into account the enhanced depletion depth caused due to the gate-fringing field at the trench oxide sidewalls and dopant redistribution in the channel. The short channel effects on the depletion charges have been taken care of while deriving this expression. This is then used to develop the model for a width-dependent threshold voltage shift. The developed model has been validated by comparing the results predicted from the derived model with experimental data as well as simulation data. In addition, the developed model has been compared with a similar model available in the literature. It has been demonstrated that our model predicts more correctly the inverse narrow width effect of nano-scale devices compared to the existing model.

A Snapback Suppressed Reverse-Conducting IGBT With a Floating p-Region in Trench Collector

A novel reverse-conducting insulated-gate bipolar transistor (RC-IGBT) featuring an oxide trench placed between the n-collector and the p-collector and a floating p-region (p-float) sandwiched between the n-drift and n-collector is proposed. First, the new structure introduces a high-resistance collector short resistor at low current density, which leads to the suppression of the snapback effect. Second, the collector short resistance can be adjusted by varying the p-float length without increasing the collector cell length. Third, the p-float layer also acts as the base of the n-collector/p-float/n-drift transistor which can be activated and offers a low-resistance current path at high current densities, which contributes to the low on-state voltage of the integrated freewheeling diode and the fast turnoff. As simulations show, the proposed RC-IGBT shows snapback-free output characteristics and faster turnoff compared with the conventional RC-IGBT.

Low on-Resistance SOI Dual-Trench-Gate MOSFET

A low specific on-resistance (Ron,sp) integrable silicon-on-insulator (SOI) MOSFET is proposed, and its mechanism is investigated by simulation. The SOI MOSFET features double trenches and dual gates (DTDG SOI): an oxide trench in the drift region, a buried gate inset in the oxide trench, and another trench gate (TG) extended to a buried oxide layer. First, the dual gates form dual conduction channels, and the extended gate widens the vertical conduction area; both of which sharply reduce Ron,sp . Second, the oxide trench folds the drift region in the vertical direction, resulting in a reduced device pitch and Ron,sp. Third, the oxide trench causes multidirectional depletion. This not only enhances the reduced surface field effect and thus reshapes the electric field distribution but also increases the drift doping concentration, leading to a reduced Ron,sp and an improved breakdown voltage (BV). Compared with a conventional SOI lateral Double-diffused metal oxide semiconductor (LDMOS), the DTDG MOSFET increases BV from 39 to 92 V at the same cell pitch or decreases Ron,sp by 77% at the same BV by simulation. Finally, the TG extended synchronously acts as an isolation trench between the high/low-voltage regions in a high-voltage integrated circuit, saving the chip area and simplifying the isolation process.

Breakdown voltage improvement of LDMOSs by charge balancing: An inserted P-layer in trench oxide (IPT-LDMOS)

For the first time, the novel inserted P-layer in trench oxide of LDMOS structure (IPT-LDMOS) is proposed in which a trench oxide with inserted P-layer is considered in the drift region to improve the breakdown voltage. Our simulation with two dimensional ALTAS simulator shows that by determining the optimum doping concentration of the P-layer, the charges of the N-drift and P-layer regions would be balanced. Therefore, complete depletion at the breakdown voltage in the drift region happens. Also, electric field in the IPT-LDMOS is modified by producing additional peaks which decrease the common peaks near the drain and source junctions.

Bulk FinFET fabrication with new approaches for oxide topography control using dry removal techniques

This work presents a process to fabricate Bulk FinFETs with advancements in critical fabrication steps such as the shallow trench oxide recess and the adjustment of the fin height. These steps are accomplished with the adoption of Siconi™ Selective Material Removal (SMR™) in the fabrication flow. FinFETs obtained with this new integration scheme were tested in a co-fabrication process flow proposed to integrate planar CMOS and Bulk FinFETs on the same wafer. Morphological and electrical results indicate perfectly filled trenches, a better fin height control and a Bulk FinFET static performance similar to planar CMOS. The 20nm wide fins are fabricated using 193nm illumination lithography followed by a series of trimming steps during the trench etching, the filling and a fin re-oxidation during the steam densification of the trench filling oxide. Trench depth is 300nm and the electrically active fin height is 40nm.

Ultra-low specific on-resistance SOI double-gate trench-type MOSFET

An ultra-low specific on-resistance (Ron, sp) silicon-on-insulator (SOI) double-gate trench-type MOSFET (DG trench MOSFET) is proposed. The MOSFET features double gates and an oxide trench: the oxide trench is in the drift region, one trench gate is inset in the oxide trench and one trench gate is extended into the buried oxide. Firstly, the double gates reduce Ron, sp by forming dual conduction channels. Secondly, the oxide trench not only folds the drift region, but also modulates the electric field, thereby reducing device pitch and increasing the breakdown voltage (BV). ABV of 93 V and a Ron, sp of 51.8 mΩ·mm2 is obtained for a DG trench MOSFET with a 3 μm half-cell pitch. Compared with a single-gate SOI MOSFET (SG MOSFET) and a single-gate SOI MOSFET with an oxide trench (SG trench MOSFET), the Ron, sp of the DG trench MOSFET decreases by 63.3% and 33.8% at the same BV, respectively.

Application of a Pelletron accelerator to study total dose radiation effects on 50 GHz SiGe HBTs

We have investigated the effects of 50 MeV lithium ion irradiation on the DC electrical characteristics of first-generation silicon–germanium heterojunction bipolar transistors (50 GHz SiGe HBTs) in the dose range of 600 krad to 100 Mrad. The results of 50 MeV Li 3+ ion irradiation on the SiGe HBTs are compared with 63 MeV proton and Co-60 gamma irradiation results in the same dose range in order to understand the damage induced by different LET species. The radiation response of emitter–base (EB) spacer oxide and shallow trench isolation (STI) oxide to different irradiation types are discussed in this paper. We have also focused on the efficacy in the application of a Pelletron accelerator to study total dose irradiation studies in SiGe HBTs.

Bias dependence of a deep submicron NMOSFET response to total dose irradiation

Deep submicron n-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs) with shallow trench isolation (STI) are exposed to ionizing dose radiation under different bias conditions. The total ionizing dose radiation induced subthreshold leakage current increase and the hump effect under four different irradiation bias conditions including the worst case (ON bias) for the transistors are discussed. The high electric fields at the corners are partly responsible for the subthreshold hump effect. Charge trapped in the isolation oxide, particularly at the Si/SiO2 interface along the sidewalls of the trench oxide creates a leakage path, which becomes a dominant contributor to the off-state drain-to-source leakage current in the NMOSFET. Non-uniform charge distribution is introduced into a three-dimensional (3D) simulation. Good agreement between experimental and simulation results is demonstrated. We find that the electric field distribution along with the STI sidewall is important for the radiation effect under different bias conditions.

Investigation of the off-State Behavior in Deep-Submicrometer NMOSFETs Under Heavy-Ion Irradiation by 3-D Simulation

The behavior of an off-state leakage current induced by heavy-ion irradiation in deep-submicrometer NMOSFETs is comprehensively investigated by 3-D simulation in this paper. The results show that the off-state drain current is increased, which is mainly due to the positively charged damage region generated by the heavy-ion strike in the shallow-trench isolation (STI) region. As the channel length scales down, the off-state leakage collapse becomes more severe. The dependence of the off-state leakage current on the device channel length and width is studied, which gives the location of the most critical physical damage region in the STI trench oxide. Moreover, the impact of the gate bias during exposure to heavy ions on the device off-state behavior is also analyzed, indicating that a low operating voltage is beneficial to the circuit radiation hardening. At last, to suppress the off-state leakage collapse, some possible solutions are proposed.

Ultralow Specific On-Resistance High-Voltage SOI Lateral MOSFET

An ultralow specific on-resistance (Ron,sp) integrable silicon-on-insulator (SOI) power lateral MOSFET is proposed. The MOSFET features double trenches: an oxide trench in the drift region and a trench gate extended to the buried oxide (BOX) (SOI DT MOSFET). First, the oxide trench causes multiple-directional depletion, which leads to electric field reshaping and an enhanced reduced surface field effect in the SOI layer. The electric field distributions in the SOI and BOX are thus improved. The oxide trench also increases the electric field strength in the x-direction due to the lower permittivity of oxide than that of Si. Both increase breakdown voltage (BV). Second, the trench makes the drift region folded in the y -direction, resulting in reduced cell pitch and Ron,sp. Third, the trench gate extended to the BOX further reduces Ron,sp by widening the vertical conduction area. The BV of the DT MOSFET increases from 91 V of the conventional SOI LDMOS to 233 V at a half-cell pitch of 6.5 μm, and the Ron,sp decreases from 5.1 to 3.3 mΩ·cm2.

Ultra-low on-resistance high voltage (> 600 V) SOI MOSFET with a reduced cell pitch

A low specific on-resistance (RS,on) silicon-on-insulator (SOI) trench MOSFET (metal—oxide—semiconductor—field—effect—transistor) with a reduced cell pitch is proposed. The lateral MOSFET features multiple trenches: two oxide trenches in the drift region and a trench gate extended to the buried oxide (BOX) (SOI MT MOSFET). Firstly, the oxide trenches increase the average electric field strength along the x direction due to lower permittivity of oxide compared with that of Si; secondly, the oxide trenches cause multiple-directional depletion, which improves the electric field distribution and enhances the reduced surface field (RESURF) effect in the SOI layer. Both of them result in a high breakdown voltage (BV). Thirdly, the oxide trenches cause the drift region to be folded in the vertical direction, leading to a shortened cell pitch and a reduced RS,on. Fourthly, the trench gate extended to the BOX further reduces RS,on, owing to the electron accumulation layer. The BV of the MT MOSFET increases from 309 V for a conventional SOI lateral double diffused metal—oxide semiconductor (LDMOS) to 632 V at the same half cell pitch of 21.5 μm, and RS,on decreases from 419 mΩ·cm2 to 36.6 mΩ·cm2. The proposed structure can also help to dramatically reduce the cell pitch at the same breakdown voltage.

Power VDMOS transistor with the step oxide trench breaks the limit line of silicon

A power vertical double-diffusion metal-oxide-semiconductor (VDMOS) transistor is designed with the step oxide trench based on the oxide-bypassed concept proposed by Liang and co-workers. It is suitable for breakdown voltage below 300 V to obtain ultra-low specific on-resistance. The electric field of the drift region is modulated because of the new electric field peak introduced by the various thicknesses of sidewall oxide. As a result, the breakdown voltage was increased no less than 20% because of more uniform electric field distribution in the drift region, while the specific on-resistance was reduced by 40–60% resulting from the step oxide trench compared with the oxide-bypassed structure. The limit line of the silicon has been broken because the trade-off is improved between the breakdown voltage and the specific on-resistance. The low Ron,sp of 15.0 mΩ mm2 with the breakdown voltage (BV) of 150 V and 28.0 mΩ mm2 with the BV of 230 V in the proposed step oxide trench MOS are improved greatly compared to the Ron,sp of 163.4 mΩ cm2 with the BV of 150 V and 475.75 mΩ mm2 with the BV of 230 V in the conventional VDMOS.

Power metal oxide semiconductor field effect transistors with accurate current sensing function over a wide temperature range

In the power metal oxide semiconductor field effect transistor (MOSFETs) with a current-sensing function (current-sensing power MOSFETs), temperature dependence in the current sense ratio has been a significant problem. The authors discuss the mechanisms involved in these temperature-dependent current sense ratios by investigating the following factors: (i) drift layer impurity concentration and layer thickness and (ii) chip size and the position of the sense MOSFET part in the chip. Furthermore, it is shown that temperature dependence in the sense ratio can be reduced by adopting a floating island and thick bottom oxide trench gate MOSFET (FITMOS) structure or by arranging the sense MOSFET part at the centre of the chip.

Improvement of floating island and thick bottom oxide trench gate metal–oxide–semiconductor field-effect transistor

A metal–oxide–semiconductor field-effect transistor (MOSFET) structure called FITMOS (floating island and thick bottom oxide trench gate MOSFET) has been successfully developed that exhibits outstanding low loss. This unique feature of the FITMOS is realised by fabricating deep trenches in the n-type drift layer, by forming p-type floating islands below the individual trenches using self-aligned ion implantation, and by fabricating trench gates with a thick oxide layer on the bottom. Then, the trade-off between the drain-to-source breakdown voltage and on-resistance has been further optimised by changing the shape of the floating islands from spherical to ellipsoidal. By improving the device structure, a breakdown voltage of 91 V and specific on-resistance of 41.5 mΩ mm2 have been obtained in a 4.5×4.5 mm square device with ellipsoidal floating islands. The relationship between the device structure and the reverse recovery characteristics is also investigated.

Development of a Nonperiodic Boundary Practical Simulator for Oxide and Shallow Trench Isolation Chemical Mechanical Polishing Processes

We developed a fast simulator for the chemical mechanical polishing (CMP) process that works in nonperiodic boundary conditions. Since periodic boundary conditions are not used, it can calculate anywhere on a wafer, such as the wafer’s edge. Additionally, we enhanced the simulator to calculate the shallow trench isolation (STI)-CMP process. In the STI-CMP simulation method, additionally required simulation parameters are only one, under the assumption that dishing reaches steady state in enough short time relative to total polishing time. We found that the simulation results could match experimental film thicknesses with an error range of about and that the calculation time was reduced to relative to when the acceleration method was not introduced.

Review on Methods for Trench MOSFET Gate Oxide Reliability and Switching Speed Improvement

In high density vertical trenched power double-diffused metal oxide semiconductor (DMOS), the trench width (CD) continually shrinks as driven by market for low cost and longer battery lifetime. Subsequently, this imposes technical challenges to keep high breakdown voltage without affecting other performances such as gate charge and on-state resistance. This paper discusses some of the technical challenges faced and suggested solutions. The various methods to improve the trench oxide uniformity and trench corner profile are also presented through experimental data. Different methods to thicken the trench bottom oxide to reduce gate-to-drain capacitance (Cgd) and eliminate the oxide weak points are introduced. This paper also reviews advanced industrial developments to increase the device switching speed as well as breakdown voltage.

Germanium on Nothing for Nanowire Devices

The authors present a fabrication process by which Germanium-on-nothing (GON) can achieve ordered arrays of locally thinned Ge nanowires for integration into CMOS or sensor applications. GON involves epitaxial Ge grown in oxide trenches on a Si substrate and then a series of wet and dry etching define the suspended wire structures. Arrays of GON nanowires, as small as 147 nm long and 48 nm wide, have been attained through this method. GON has the potential to monolithically integrate Ge NWs for transistor and NEMS applications on a Si substrate.