Transmission Gate Research Articles

Design of high speed and low power 4-bit comparator using FGMOS

This paper presents a novel low power and high speed 4-bit comparator extendable to 64-bits using floating-gate MOSFET (FGMOS). Here, we have exploited the unique feature of FGMOS wherein the effective voltage at its floating-gate is the weighted sum of many input voltages which are capacitively coupled to the floating-gate. The performance of proposed 4-bit comparator circuit has been compared with other comparator circuits designed using CMOS, transmission gate (TG), pass transistor logic (PTL) and gate diffusion input (GDI) technique. The proposed FGMOS based 4-bit comparator have shown remarkable performance in terms of transistor count, speed, power dissipation and power delay product besides full swing at the output in comparison to the existing comparator designs available in literature. Thus the proposed circuit can be viable option for high speed and low power applications. The performance of the proposed FGMOS based 4-bit comparator has been verified through OrCAD PSpice simulations through circuit file/schematics using level 7 parameters obtained from TSMC in 0.13μm technology with the supply voltage of 1V.

10T SRAM Using Half- $V_{\text {DD}}$ Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage

We present, in this paper, a new 10T static random access memory cell having single ended decoupled read-bitline (RBL) with a 4T read port for low power operation and leakage reduction. The RBL is precharged at half the cell’s supply voltage, and is allowed to charge and discharge according to the stored data bit. An inverter, driven by the complementary data node (QB), connects the RBL to the virtual power rails through a transmission gate during the read operation. RBL increases toward the $V_{\text {DD}}$ level for a read-1, and discharges toward the ground level for a read-0. Virtual power rails have the same value of the RBL precharging level during the write and the hold mode, and are connected to true supply levels only during the read operation. Dynamic control of virtual rails substantially reduces the RBL leakage. The proposed 10T cell in a commercial 65 nm technology is $2.47\times $ the size of 6T with $\beta = 2$ , provides $2.3\times $ read static noise margin, and reduces the read power dissipation by 50% than that of 6T. The value of RBL leakage is reduced by more than 3 orders of magnitude and $({I_{\mathrm{\scriptscriptstyle ON}}}/{I_{\mathrm{\scriptscriptstyle OFF}}})$ is greatly improved compared with the 6T BL leakage. The overall leakage characteristics of 6T and 10T are similar, and competitive performance is achieved.

Design of Three-Input XOR/XNOR Using Systematic Cell Design Methodology

The rapid growths of portable electronic devices are increased and they are designing with low power and high speed is critical. To design a three input XOR and XNOR gates using the systematic cell design methodology can be achieved by implementing transmission gate. By this type of designing the low power and high speed can achieved. This architecture is used to maintain summation results for after completing addition process. XOR/XNOR circuits are proposed with high driving capability, full-balanced full-swing outputs and low number transistors of basic structure, high performance and operating at low voltages. This simulation is carried out using TSMC 90nmCMOS technology in Tanner EDA Tool.

Design of transmission gate using electro-optic effect of lithium niobate based Mach–Zehnder interferometers

Optical integrated circuits for computing and information processing could overcome the speed limitations of semiconductor electronics. However, in photonics, very few fundamental building blocks equivalent to those used in multi-functional electronic circuits exist. In this paper, transmission gate based on electro-optic effect inside lithium niobate based Mach–Zehnder interferometers (MZI) is described. Transmission gates are typically used as building blocks for logic circuitry in integrated circuit design. It is a combination of NMOS and PMOS transistors. Lithium niobate based MZI has a phenomenal competence to switching optical signal to a desired output port. Here, proposed device is elucidated with the help of mathematical description and thereafter simulation using MATLAB. 2 \(\times \) 1 multiplexer is also designed using proposed transmission gate. The study is verified using beam propagation method.

Enhancing Tumor Detection in IR-UWB Breast Cancer System.

An ultra-wideband (UWB) microwave system for breast cancer detection is presented. The proposed system includes monocycle pulse generator, antipodal Vivaldi antenna, breast model, and calibration algorithm for tumor detection. Firstly, our pulse generator employs transmission gate in glitch generator to achieve several advantages such as low power consumption and low ringing level. Secondly, the antipodal Vivaldi antenna is designed assuming FR4 dielectric substrate material, and developed antenna element (80 × 80 mm2) features a −10 dB return loss and bandwidth ranges from 2.3 GHz to more than 11 GHz. Thirdly, the phantom breast can be modeled as a layer of skin, fat, and then tumor is inserted in this layer. Finally, subtract and add algorithm (SAD) is used as a calibration algorithm in tumor detection system. The proposed system suggested that horizontal antenna position with 90° between transmitting and receiving antennas is localized as a suitable antenna position with different rotating location and a 0.5 cm near to phantom. The mean advantages of this localization and tracking position around breast is a high received power signal approximately around mv as a higher recognized signal in tumor detection. Using our proposed system we can detect tumor in 5 mm diameter.

Programmable Input Mode Instrumentation Amplifier Using Multiple Output Current Conveyors

Abstract In this paper a programmable input mode instrumentation amplifier (IA) utilising second generation, multiple output current conveyors and transmission gates is presented. Its main advantage is the ability to choose a voltage or current mode of inputs by setting the voltage of two configuration nodes. The presented IA is prepared as an integrated circuit block to be used alone or as a sub-block in a microcontroller or in a field programmable gate array (FPGA), which shall condition analogue signals to be next converted by an analogue-to-digital converter (ADC). IA is designed in AMS 0.35 µm CMOS technology and the power supply is 3.3 V; the power consumption is approximately 9.1 mW. A linear input range in the voltage mode reaches ± 1.68 V or ± 250 µA in current mode. A passband of the IA is above 11 MHz. The amplifier works in class A, so its current supply is almost constant and does not cause noise disturbing nearby working precision analogue circuits.

Current Steering Digital Analog Converter with Partial Binary Tree Network (PBTN)

DACs are essential devices in many digital systems which require high performance data converters. Thus, shrinking of supply voltage, budget constraints of test times, and rising bandwidth requirement causing DAC architectures to highly relying on matched components to perform data conversions. However, matched components are nearly impossible to fabricate; there are always mismatch errors which causes the difference between the designed and actual component value. Dynamic Element Matching (DEM) is one of the techniques that are commonly used to reduce component mismatch error. This technique is a randomization technique to select one of the appropriate codes for each of the digital input value before entering DAC block. Thus, in this research, a new DEM algorithm is proposed on Current-Steering DAC with Partial Binary Tree Network (PBTN) algorithm that utilizes a lower complexity circuit to produce output signals with less glitches. Simulation results for 6-bit 1-MSB PBTN DAC produces 0.3184LSB of DNL, 0.0062LSB of INL, and a power consumption of 14.13 mW, while using only 126 transmission gates.

A novel nanoscaled Schottky barrier based transmission gate and its digital circuit applications

In this work we propose and simulate a compact nanoscaled transmission gate (TG) employing a single Schottky barrier based transistor in the transmission path and a single transistor based Sajad-Sunil-Schottky (SSS) device as an inverter. Therefore, just two transistors are employed to realize a complete transmission gate which normally consumes four transistors in the conventional technology. The transistors used to realize the transmission path and the SSS inverter in the proposed TG are the double gate Schottky barrier devices, employing stacks of two metal silicides, platinum silicide (PtSi) and erbium silicide (ErSi). It has been observed that the realization of the TG gate by the proposed technology has resulted into a compact structure, with reduced component count, junctions, interconnections and regions in comparison to the conventional technology. The further focus of this work is on the application part of the proposed technology. So for the first time, the proposed technology has been used to realize various combinational circuits, like a two input AND gate, a 2:1 multiplexer and a two input XOR circuits. It has been observed that the transistor count has got reduced by half in a TG, two input AND gate, 2:1 multiplexer and in a two input XOR gate. Therefore, a significant reduction in transistor count and area requirement can be achieved by using the proposed technology. The proposed technology can be also used to perform the compact realization of other combinational and sequential circuitry in future.

Soft Error Mitigation Using Transmission Gate With Varying Gate and Body Bias

Soft errors not only are major threats to SRAM, but also have become a major threat to the reliability of logic circuits. This article proposes a new transmission-gate approach to filter out soft errors, and it is more efficient when to the thanks to its to compared state of art solutions, capability adjust gate and body bias voltages.

Design of Low-Power High-Performance 2–4 and 4–16 Mixed-Logic Line Decoders

This brief introduces a mixed-logic design method for line decoders, combining transmission gate logic, pass transistor dual-value logic, and static complementary metal-oxide semiconductor (CMOS). Two novel topologies are presented for the 2-4 decoder: a 14-transistor topology aiming on minimizing transistor count and power dissipation and a 15-transistor topology aiming on high power-delay performance. Both normal and inverting decoders are implemented in each case, yielding a total of four new designs. Furthermore, four new 4-16 decoders are designed by using mixed-logic 2-4 predecoders combined with standard CMOS postdecoder. All proposed decoders have full-swinging capability and reduced transistor count compared to their conventional CMOS counterparts. Finally, a variety of comparative spice simulations at 32 nm shows that the proposed circuits present a significant improvement in power and delay, outperforming CMOS in almost all cases.

Set/reset reference and parasitic matching scheme to speed up PCM read operation

Three kinds of parameters are considered to speed up the read operation of phase change memory: bit line parasitic parameters, read transmission gate parasitic parameters and current mirror parasitic parameters. A set reference cell and a reset reference cell are used in the reference circuit. Simulated in 130 nm process, the read access time of 1-Mb phase change memory (PCM) is 6.7 ns. In Monte Carlo simulations, the worst read access time is 13.8 ns compared to conventional 85 ns.

Memristor-Based Low-Power High-Speed Nonvolatile Hybrid Memory Array Design

In this paper, a memristor–transistor hybrid architecture-based nonvolatile memory array design approach has been proposed. Here, a single memory cell consists of a memristor and one transmission gate, whereas a conventional SRAM cell consists of six transistors. This proposed design has the advantage of being nonvolatile, having high switching speed and low power requirement. The proposed cell shows better performance in comparison with other published memristor–transistor hybrid memory cell.

Design and Implementation of Low Power Hybrid 1Bit Full Adder

Design of one-bit hybrid full adder plan utilizing equally the reciprocal metal-oxide-semiconductor (CMOS) logic and transmission gate logic is accounted for. The outline was initially executed for one bit and it extended to 32-bit moreover. The designed circuit was executed utilizing Cadence Virtuoso devices as a part of 180-furthermore, 90-nm technology. power, delay, and layout area are the parameter considered during the execution were contrasted and the current outlines for example, complementary passtransistor logic, transmission function adder, transmission capacity adder, hybrid pass-logic with static CMOS yield drive full adder. For 1.8-V supply at 180-nm technology, the normal force utilization (4.1563 μW) was observed to be to a great degree small with decently less delay(224 ps) coming about because of the conscious incorporation of extremely frail CMOS inverters combined with tough transmission gates. Consequent estimations of the similar were 1.17564 μW and 91.5 ps at 90-nm technology working at 1.2-V supply voltage. The design was further reached out for implementing the 32-bit full adder likewise, and was observed to work proficiently with just 5.578-ns (2.45-ns) delay furthermore, 112.69-μW (53.26-μW) power at 180-nm (90-nm) technology for 1.8-V (1.2-V) supply voltage. In correlation with the current full adder design, the present usage offer reduction of power and improve the speed of the design.

A 12T MT-CMOS low power and low leakage SRAM cell

This paper focuses on the design of low power and stable, novel 12T multi-threshold CMOS (MTCMOS)-based static random access memory (SRAM) cell. In the proposed structure two voltage sources are used, one connected with the bit line and the other one connected with the bitbar line in order to reduce the swing voltage at the output nodes of the bit and the bitbar lines. Reduction in swing voltage reduces the dynamic power dissipation. Low threshold voltage (LVT) transmission gate (TG) and two high threshold voltage (HVT) sleep transistors are used for applying the charge recycling technique. The charge recycling technique reduces leakage current when the transistors change its state from sleep-to-active (OFF-to-ON condition) and active-to-sleep (ON-to-OFF condition) modes. Reduction in leakage current causes the reduction in static power dissipation. So in the proposed SRAM cell both dynamic and static powers have been reduced. Stability of the proposed SRAM has also improved due to the reduction in swing voltage. The circuit simulation has been done in 45 nm CMOS environment. Microwind 3.1 is used for the purpose of schematic and layout designs.

On Improving the Performance of Dynamic DCVSL Circuits

This contribution aims at improving the performance of Dynamic Differential Cascode Voltage Switch Logic (Dy-DCVSL) and Enhanced Dynamic Differential Cascode Voltage Switch Logic (EDCVSL) and suggests three architectures for the same. The first architecture uses transmission gates (TG) to reduce the logic tree depth and width, which results in speed improvement. As leakage is a dominant issue in lower technology nodes, the second architecture is proposed by adapting the leakage control technique (LECTOR) in Dy-DCVSL and EDCVSL. The third proposed architecture combines features of both the first and the second architectures. The operation of the proposed architectures has been verified through extensive simulations with different CMOS submicron technology nodes (90 nm, 65 nm, and 45 nm). The delay of the gates based on the first architecture remains almost the same for different functionalities. It is also observed that Dy-DCVSL gates are 1.6 to 1.4 times faster than their conventional counterpart. The gates based on the second architecture show a maximum of 74.3% leakage power reduction. Also, it is observed that the percentage of reduction in leakage power increases with technology scaling. Lastly, the gates based on the third architecture achieve similar leakage power reduction values to the second one but are not able to exhibit the same speed advantage as achieved with the first architecture.

A 12T MT-CMOS low power and low leakage SRAM cell

This paper focuses on the design of low power and stable, novel 12T multi-threshold CMOS (MTCMOS)-based static random access memory (SRAM) cell. In the proposed structure two voltage sources are used, one connected with the bit line and the other one connected with the bitbar line in order to reduce the swing voltage at the output nodes of the bit and the bitbar lines. Reduction in swing voltage reduces the dynamic power dissipation. Low threshold voltage (LVT) transmission gate (TG) and two high threshold voltage (HVT) sleep transistors are used for applying the charge recycling technique. The charge recycling technique reduces leakage current when the transistors change its state from sleep-to-active (OFF-to-ON condition) and active-to-sleep (ON-to-OFF condition) modes. Reduction in leakage current causes the reduction in static power dissipation. So in the proposed SRAM cell both dynamic and static powers have been reduced. Stability of the proposed SRAM has also improved due to the reduction in swing voltage. The circuit simulation has been done in 45 nm CMOS environment. Microwind 3.1 is used for the purpose of schematic and layout designs.

An Efficient Design and Analysis of Low Power SRAM Memory Cell for Ultra Applications

Power consumption is the fundamental design constraint in Very Large Scale Integration (VLSI) technology with the improvement in transistor counts and clock frequencies. This paper introduces techniques for originating Static Random Access Memory (SRAM) cell with low power and delay. The proposed 6T SRAM cell uses self-controllable voltage level-upper (SVL-U) method and transmission gate logic with the reduction in dynamic power by 68% on an average related to conventional techniques. The proposed 7T SRAM cell works adiabatic technique which diminishes the dynamic power by 84% on an average compared to conventional techniques. Parameters like delay and power-delay product (PDP) are determined and the simulation is executed using Tanner EDA tool at 250nm, 180nm, and 45nm technologies.

Design of Low Leakage Current Average Power CMOS Current Comparator Using SVL Technique With Pseudo NMOS and Transmission Gate Logics

Abstract Comparatorare most widely used second electronic components after operational amplifier. For ADC circuit we have to use the high speed and low power consumption based comparator. SVL circuit is used tom reduce the offset voltage which requires high voltage gain. A SVL circuit can supply maximum DC voltage to an active load circuit on request or can decrease the DC voltage supplied to a load circuit in the standby mode was developed. SVL circuit is used with comparator which reduce the power consumption from 258.6μw to 156.7μw. Pseudo nmos logic and transmission gate logic is used with the SVL based current comparator which further reduce the power consumption in the standby mode. This technique based comparator is fabricated on the tanner tool of 45nm technology.SVL technique is mostly recommended for CMOS logic.

An integrated DFT solution for power reduction in scan test applications by low power gating scan cell

Shrinking technologies to deep sub-microns has raised demands for high quality testing. However, excessive power during test application time serves as limiting factors for reliability in testing. To address these issues, we have proposed Integrated Low Power Gating (ILPG) Scan Cell to alleviate shift power consumption by modifying conventional master-slave scan cell. It is able to reduce power consumption inside the scan cell as well as to gate the redundant transitions propagation from scan chain to combinational part during shifting. Another low power gating scan cell for critical paths, called Critical Path Integrated Low Power Gating (CPILPG) Scan Cell, has been proposed. It speeds up the data launch operation in normal/capture mode compared to ILPG scan cell through the utilization of transmission gate. Both designs use a shorter shift path to improve critical path delay and reduce power in scan chain. This allows shift frequency increase further within maximum power budget. Hence, test application time is shortened. Our post-layout experiment results show an average power reduction of 15.12% for ILPG over conventional scan cell and up to 39.15% improvement compared to one of the most popular gating techniques. In addition, 51.42% and 43.94% improvements in CLK-to-shift delay over conventional scan cell are achieved for ILPG and CPILPG, respectively.

Teaching Practice for CMOS Inverter and Transmission Gate

CMOS inverter and transmission gate are the basic logic gate circuits in digital logic design and its application. They are also the digital circuits with which students first come into contact. Correctly understanding the inverter and the gate is the basis of learning other logic gate circuits. From the question existed in NMOS inverter to the formation of CMOS inverter and transmission gate, heuristic and discussion-based teaching method is applied in the course teaching. The process of problem solving is presented by guiding the students to analyze problems step by step. The practice results have shown that students’ interest in learning the course has been improved, and that the knowledge of context and the related knowledge of mutual relations have been mastered.