Design and Implementation of Low Power Hybrid 1Bit Full Adder

Abstract

Design of one-bit hybrid full adder plan utilizing equally the reciprocal metal-oxide-semiconductor (CMOS) logic and transmission gate logic is accounted for. The outline was initially executed for one bit and it extended to 32-bit moreover. The designed circuit was executed utilizing Cadence Virtuoso devices as a part of 180-furthermore, 90-nm technology. power, delay, and layout area are the parameter considered during the execution were contrasted and the current outlines for example, complementary passtransistor logic, transmission function adder, transmission capacity adder, hybrid pass-logic with static CMOS yield drive full adder. For 1.8-V supply at 180-nm technology, the normal force utilization (4.1563 μW) was observed to be to a great degree small with decently less delay(224 ps) coming about because of the conscious incorporation of extremely frail CMOS inverters combined with tough transmission gates. Consequent estimations of the similar were 1.17564 μW and 91.5 ps at 90-nm technology working at 1.2-V supply voltage. The design was further reached out for implementing the 32-bit full adder likewise, and was observed to work proficiently with just 5.578-ns (2.45-ns) delay furthermore, 112.69-μW (53.26-μW) power at 180-nm (90-nm) technology for 1.8-V (1.2-V) supply voltage. In correlation with the current full adder design, the present usage offer reduction of power and improve the speed of the design.