Transistor Turn-on Research Articles

Energy Storage and Reuse in Negative Capacitance

In this article, we analyze how a ferroelectric (FE) acts as a rechargeable energy storage medium which stores, releases, and retrieves energy, and helps the gate achieve a desired charge density with reduced energy (voltage) from the external gate drive. During transistor turn-on, the FE releases energy, while the whole system is absorbing energy, and during turn-off, the FE retrieves energy, while the whole system is releasing energy. Capacitor energy is analyzed using two different approaches: static material free energy integrals and transient circuit power integrals. The two results agree within 1%. Energy analysis is also performed for a metal–oxide–semiconductor field-effect transistor structure for two gate lengths, 20 nm and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2~\mu \text{m}$ </tex-math></inline-formula> , in an inverter circuit. At 2- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> gate length, the values of energy match under these two different approaches with less than a 6% difference. The difference is larger in the 20-nm gate length case due to larger parasitic capacitances, such as gate-to-drain and gate-to-source capacitance, affecting the transient circuit analysis. Even so, most of the energy storage and retrieval benefit is retained even in small size negative capacitance transistors.

A Power-Aware Toggling-Frequency Actuator in Data-Toggling SRAM for Secure Data Protection

We propose a power-aware toggling-frequency actuator for an 1K-byte data-toggling SRAM. The actuator periodically toggles the stored data to balance the voltage stress in the SRAM cells to secure against data imprinting attacks. Our proposed actuator has three key features. First, our proposed actuator embodies a small duty cycle clock divider to divide the main clock and generate two toggling clocks. The small duty cycle clock minimizes toggling transistor turn-on time and reduces the leakage power in stand-by operation. Second, it leverages on the main clock of the data-toggling SRAM to generate the toggling clock without an additional clock generator. Third, our proposed actuator can scale the data toggling operation between high frequency for highly secure applications, and low frequency for low power applications. We implemented the 1K-byte data-toggling SRAM with the proposed toggling-frequency actuator based on 65nm CMOS technology. At higher toggling frequency (~ 1MHz), the data-toggling SRAM features less than 5% imprinting effect. At lower toggling frequency (~ 10kHz), the SRAM dissipates <; 0.1mW toggling power where the secure data protection is less critical. When compared against the reported counterpart with toggling clock of 50% duty cycle, our proposed data-toggling SRAM (with ~ 3% duty cycle clock divider) occupies ~ 31% smaller IC area and dissipates ~ 29% lower toggling power, resulting in an overall reduction of ~ 51% area ×power product.

Power Loss Comparison in a BOOST PFC Circuit Considering the Reverse Recovery of the Forward Diode

The nature of diode reverse recovery is analyzed in this paper, and the reverse recovery loss is evaluated in a BOOST PFC converter using a silicon (Si) or silicon carbide (SiC) diode in the forward branch. Mathematical models of the forward conduction and reverse recovery losses are established to assess the influence of Si and SiC diodes. To characterize and quantify the losses related to diode reverse recovery, an 85~265V AC to 400V DC, 2kW BOOST PFC prototype is built with switching frequencies of 65kHz. It is found that the reverse-recovery inherent in a Si diode cannot be neglected. The switching loss is substantially smaller when the diode is a SiC one. In order to investigate further, a double pulse test rig is established, with the switch and the diode being either Si or SiC. The experimental results demonstrate that with a SiC diode, not only the diode conduction losses but also the transistor turn-on loss is greatly reduced.

Improving Linearity and Robustness of RF LDMOS by Mitigating Quasi-Saturation Effect

This paper discusses linearity and robustness together for the first time, disclosing a way to improve them. It reveals that the nonlinear transconductance with device working at quasi-saturation region is significant factor of device linearity. The peak electric field is the root cause of electron velocity saturation. The high electric field at the drift region near the drain will cause more electron-hole pairs generated to trigger the parasitic NPN transistor turn-on, which may cause failure of device. Devices with different drift region doping are simulated with TCAD and measured. With LDD4 doping, the peak electric field in the drift region is reduced; the linear region of the transconductance is broadened. The adjacent channel power ratio is decreased by 2 dBc; 12% more power can be discharged before the NPN transistor turn-on, indicating a better linearity and robustness.

Single-Event Burnout Mechanisms in SiC Power MOSFETs

Heavy ion-induced single-event burnout (SEB) is investigated in high-voltage silicon carbide power MOSFETs. Experimental data for 1200-V SiC power MOSFETs show a significant decrease in SEB onset voltage for particle linear energy transfers greater than 10 MeV/cm2/mg, above which the SEB threshold voltage is nearly constant at half of the rated maximum operating voltage for these devices. TCAD simulations show a parasitic bipolar junction transistor turn-on mechanism, which drives the avalanching of carriers and leads to runaway drain current, resulting in SEB.

The Dipole Moment Inversion Effects in Self-Assembled Nanodielectrics for Organic Transistors

We compare and contrast the properties of hybrid organic–inorganic self-assembled nanodielectrics (SANDs) based on alternating layers of solution-processed ZrOx and either of two phosphonic acid-functionalized azastilbazolium π-units having opposite dipolar orientations. Conventional Zr-SAND and new inverted IZr-SAND are characterized by Kevin probe, optical spectroscopy, capacitance–voltage measurements, AFM, X-ray reflectivity, and electronic structure computation. The molecular dipolar orientation affects thin-film transistor (TFT) threshold and turn-on voltages for devices based on either p-channel pentacene or n-channel copper perfluorophthalocyanine. Specifically, Zr-SAND shifts the threshold and turn-on voltages to more positive values, whereas IZr-SAND shifts them in the opposite direction. Capping these SANDs with −SiMe3 groups enhances the effect, affording a 1.3 V difference in turn-on voltage for IZr-SAND vs Zr-SAND-gated organic TFTs. Such tunability should facilitate the engineering of more ...

The influence of interfacial defects on fast charge trapping in nanocrystalline oxide-semiconductor thin film transistors

Defects in oxide semiconductors not only influence the initial device performance but also affect device reliability. The front channel is the major carrier transport region during the transistor turn-on stage, therefore an understanding of defects located in the vicinity of the interface is very important. In this study, we investigated the dynamics of charge transport in a nanocrystalline hafnium-indium-zinc-oxide thin-film transistor (TFT) by short pulse I–V, transient current and 1/f noise measurement methods. We found that the fast charging behavior of the tested device stems from defects located in both the front channel and the interface, following a multi-trapping mechanism. We found that a silicon-nitride stacked hafnium-indium-zinc-oxide TFT is vulnerable to interfacial charge trapping compared with silicon-oxide counterpart, causing significant mobility degradation and threshold voltage instability. The 1/f noise measurement data indicate that the carrier transport in a silicon-nitride stacked TFT device is governed by trapping/de-trapping processes via defects in the interface, while the silicon-oxide device follows the mobility fluctuation model.

Pulsed voltage multiplier based on printed organic devices

To enable the integration of components with different supply voltage requirements, and to optimize power consumption in printed flexible electronics, we demonstrate an inkjet-printed pulsed voltage multiplier that boosts the voltage at specific circuit nodes above the supply voltage. A five-stage pulsed voltage multiplier is shown to provide an output voltage up to 18 V from a supply voltage of 10 V, with minimum 10 ms pulse rise time for a 70 pF load. This circuit allows a single power source to deliver multiple voltage levels and enables integration of low-voltage logic with components that require higher operating voltage. A key requirement for the pulsed voltage multiplier circuit is low device leakage to boost the output voltage level. To this end, the composition of the transistor semiconducting layer is modified by blending an insulating polymer with the small molecule semiconductor. This modification allows control over the transistor turn-on voltage, which enables low leakage current required for operation of the circuit.

Chip Technology Based on High Efficiency DC Power Supply

The switching power supply is the use of modern power electronics, by controlling the switching transistor turn-on and turn-off time ratio, maintaining a stable output voltage of the power supply. Switching power supply technology at the core, it is mainly divided into AC / DC and DC / DC two categories. Switching power supply eliminates bulky frequency transformers, replacing tens of kHz, MHz or even hundreds of kHz frequency transformer. Since the adjustment pipe work in the off state, and thus low power consumption and high efficiency.

Low-Voltage Steep Turn-On pMOSFET Using Ferroelectric High-$\kappa$ Gate Dielectric

Power consumption is the most difficult challenge for CMOS integrated circuits. Here, we demonstrate experimentally a novel steep turn-on pMOSFET for low-voltage operation for the first time, which exhibits 5-60 mV/decade SS, wide voltage range for , sturdy SS at 85°C, faster transistor turn-on at above threshold voltage, and lower off-state leakage by greater than three orders of magnitude. Such improved leakage current is crucial to decrease the OFF-state leakage current in sub-1X nm CMOS. This was achieved using ferroelectric high-κ ZrHfO gate dielectric pMOSFET.

Total ionising dose effects on punch-through insulated gate bipolar transistors turn-on switching behaviour

This paper deals with the effects of 60Co gamma irradiation on punch-through commercial insulated gate bipolar transistor turn-on switching behaviour. The response of the threshold voltage and the turn-on switching parameters under three different in situ gate biases are described. Charge trapping in the gate oxide causes the decrease of the threshold voltage. It is shown that the decrease of this parameter and the decrease of the Miller plateau level result in a decrease of the collector current rise-time, the collector–emitter voltage fall-time, the turn-on switching energy and in an increase of the peak of the turn-on switching instantaneous power and of the turn-on overshoot collector current.

Self-Aligned Silicidation of Surround Gate Vertical MOSFETs for Low Cost RF Applications

We report for the first time a CMOS-compatible silicidation technology for surround-gate vertical MOSFETs. The technology uses a double spacer comprising a polysilicon spacer for the surround gate and a nitride spacer for silicidation and is successfully integrated with a Fillet Local OXidation (FILOX) process, which thereby delivers low overlap capacitance and high-drive-current vertical devices. Silicided 80-nm vertical n-channel devices fabricated using 0.5-μm lithography are compared with nonsilicided devices. A source-drain (S/D) activation anneal of 30 s at 1100°C is shown to deliver a channel length of 80 nm, and the silicidation gives a 60% improvement in drive current in comparison with nonsilicided devices. The silicided devices exhibit a subthreshold slope (S) of 87 mV/dec and a drain-induced barrier lowering (DIBL) of 80 mV/V, compared with 86 mV/dec and 60 mV/V for nonsilicided devices. S-parameter measurements on the 80-nm vertical nMOS devices give an fT of 20 GHz, which is approximately two times higher than expected for comparable lateral MOSFETs fabricated using the same 0.5-μm lithography. Issues associated with silicidation down the pillar sidewall are investigated by reducing the activation anneal time to bring the silicided region closer to the p-n junction at the top of the pillar. In this situation, nonlinear transistor turn-on is observed in drain-on-top operation and dramatically degraded drive current in source-on-top operation. This behavior is interpreted using mixed-mode simulations, which show that a Schottky contact is formed around the perimeter of the pillar when the silicided contact penetrates too close to the top S/D junction down the side of the pillar.

Application of a novel test system to characterize single-event effects at cryogenic temperatures

Details of a customized cryogenic test system for use in in situ single-event radiation tests on semiconductor devices at cryogenic temperatures are presented. The lightweight portable system is designed for performing heavy-ion broadbeam single-event radiation testing at different beam facilities. It is designed for use with either liquid nitrogen or liquid helium as cryogens, depending on the desired lower temperature limit. A controlled heating system on the inside allows for single-event radiation tests as a function of temperature. To enable single-event strikes at angles, the device under test can be rotated about a vertical axis without having to break vacuum. Electrical connectivity to the device under test is provided through six fully customizable hermetically sealed connecting ports. The system has been used to conduct single-event tests over temperature on a test circuit fabricated in IBM CMOS 130 nm technology. Single-event transient pulse widths were found to increase by up to 30% as the temperature was varied from −135 °C to +20 °C. Device simulations indicate that single-event-induced parasitic bipolar transistor turn-on in the n-well of PMOS transistors is responsible for the observed increase in pulse widths across the temperature ranges considered.

ESD performance of 65 nm partially depleted n and p channel SOI MOSFETs

A study on the electrostatic discharge (ESD) behaviors of silicide blocked (Sblk) n and p channel MOSFETs is presented for a state-of-the-art 65nm SOI technology. It is observed that the charge in the floating body SOI MOSFETs helps to improve their ESD characteristics over the grounded body devices. The ESD behavior of the thin-oxide pMOSFETs shows failure current similar to the corresponding nMOSFETs but at the expense of higher power dissipation and higher parasitic bipolar transistor (pBJT) turn-on voltages. The study of gate-silicided (GS) and gate-non-silicided (GNS) nMOSFETs show that the GNS devices exhibit approximately 30% higher failure current than the similar sized GS devices. Transmission line pulsing (TLP) measurement with different stress pulse widths reveals that the self-heating effects are more pronounced in the GNS devices than the similar sized GS devices. The analytical thermal model for the bulk MOSFET when applied to the SOI MOSFET indicates that the high temperature region during the breakdown is not only at the drain-body junction but extends into the highly resistive drain silicide-blocked region.

Polaron and ion diffusion in a poly(3-hexylthiophene) thin-film transistor gated with polymer electrolyte dielectric

Electrolytes are finding applications as dielectric materials in low-voltage organic thin-film transistors (OTFT). The presence of mobile ions in these materials (polymer electrolytes or ion gels) gives rise to very high capacitance (>10 μF/cm2) and thus low transistor turn-on voltage. In order to establish fundamental limits in switching speeds of electrolyte gated OFETs, we carry out in situ optical spectroscopy measurement of a poly(3-hexylthiophene) (P3HT) OTFT gated with a LiClO4:poly(ethyleneoxide) (PEO) dielectric. Based on spectroscopic signatures of molecular vibrations and polaron transitions, we quantitatively determine charge carrier concentration and diffusion constants. We find two distinctively different regions: at VG≥−1.5 V, drift-diffusion (parallel to the semiconductor/dielectric interface) of hole-polarons in P3HT controls charging of the device; at VG<−1.5 V, electrochemical doping of the entire P3HT film occurs and charging is controlled by drift/diffusion (perpendicular to the interface) of ClO4− counter ions into the polymer semiconductor.

The influence of bulk traps on the subthreshold characteristics of an organic field effect transistor

The subthreshold characteristics of fabricated organic field effect transistors based on regioregular poly(3-dodecylthiophene) (P3DDT) as the active layer and poly-4-vinylphenol (P4VP) as the gate insulator have been investigated. The transistor turn-on occurs at a threshold voltage of around V th=0 V. The (hole) mobility of 0.002–0.005 cm 2/(V s) has been estimated from the linear region of the transfer characteristics. As usually observed for organic transistors, the inverse subthreshold slope is very high, in our case S≈7 V/dec. Furthermore, the subthreshold current depends on the drain voltage although the transistor is a long channel device. One possibility to explain these peculiarities are interface traps, as demonstrated recently by Scheinert et al. [J. Appl. Phys. 92 (2002) 330]. In this paper, the influence of bulk traps is shown. It turns out that both the high inverse subthreshold slope and the drain voltage dependence can be explained also by recharging of bulk traps. Therefore, other frequency and temperature dependent dynamic measurements have to be applied to distinguish between the different possible influences.

Subthreshold characteristics of field effect transistors based on poly(3-dodecylthiophene) and an organic insulator

The properties of field effect transistors with organic insulator and semiconducting regions, fabricated with a top-gate architecture, have been investigated. Thin films (d≈30 nm) of regioregular poly(3-dodecylthiophene) were employed as the active semiconductor and the gate insulator was formed by a 500-nm-thick layer of poly(4-vinylphenol). Both were solution-processed on top of poly(ethylenetherephthalate) films, which were used as substrates. The output characteristics show a pronounced saturation behavior with an unconventional nonquadratic saturation current dependence on the gate voltage. Hence the (hole) mobility of 0.002–0.005 cm2/Vs has been estimated from the linear region of the transfer characteristics. The transistor turn-on occurs at a threshold voltage of approximately Vth=0 V, and the device can be operated with a supply voltage of between 15 and 20 V. As is usually observed for organic transistors, the inverse subthreshold slope (S) is very high, in our case S≈7 V/dec, by contrast with S≈200 mV/dec obtained for the similar material poly(3-octylthiophene) (P3OT) with silicon dioxide (SiO2) as an insulator. Furthermore, the subthreshold current depends on the drain voltage even though the transistor is electrically a long channel device with L=2 μm, notwithstanding the fact that this channel length is rather small for the present organic devices. To clarify these peculiarities numerical simulations have been carried out with a systematic variation of the relevant material parameters and assuming the existence of interface or bulk trap states. It turns out that both the high inverse subthreshold slope and the drain voltage dependence can be explained by recharging of trap states either at the interface or in the bulk. Considering the difference to the P3OT device with SiO2 as insulator it is proposed that interface traps are responsible for these effects, although one excludes the possibility that the film formation either on an organic substrate or on SiO2 leads to different bulk properties.

Short-Channel Effect Suppression In Silicon Carbide Power Mesfets

ABSTRACTWe demonstrate that the performance of silicon carbide MESFETs is largely determined by short-channel effects. Parasitic bipolar transistor turn-on limits the operation voltage to a small fraction of the theoretically expected value for an ideal device. Tradeoffs are shown to exist between optimum gate length and on-state current on one hand, and the maximum blocking voltage on the other hand. Composite p-buffers with an elevated doping in the vicinity of the active layer considerably increase the operation voltage. Silicon carbide MESFETs utilizing composite buffers are reported.

Designing 1-V op amps using standard digital CMOS technology

This paper addresses the difficulty of designing 1-V capable analog circuits in standard digital complementary metal-oxide-semiconductor (CMOS) technology, Design techniques for facilitating 1-V operation are discussed and 1-V analog building block circuits are presented. Most of these circuits use the bulk-driving technique to circumvent the metal-oxide-semiconductor field-effect transistor turn-on (threshold) voltage requirement. Finally, techniques are combined within a 1-V CMOS operational amplifier with rail-to-rail input and output ranges. While consuming 300 /spl mu/W, the 1-V rail-to-rail CMOS op amp achieves 1.3-MHz unity-gain frequency and 57/spl deg/ phase margin for a 22-pF load capacitance.

Scaling constraints imposed by self-heating in submicron SOI MOSFET's

The presence of a buried oxide layer in silicon causes enhanced self-heating in Silicon-On-Insulator (SOI) n-channel MOSFETs. The self-heating becomes more pronounced as device dimensions are reduced into the submicron regime because of increased electric field density and reduced silicon volume available for heat removal. Two-dimensional numerical simulations are used to show that self-heating manifests itself in the form of degraded drive current due to mobility reduction and premature breakdown. The heat flow equation was consistently solved with the classical semiconductor equations to study the effect of power dissipation on carrier transport. The simulated temperature increases in the channel region are shown to be in close agreement with recently measured data. Numerical simulation results also demonstrated accelerated turn-on of the parasitic bipolar transistor due to self-heating. Simulation results were used to identify scaling constraints caused by the parasitic bipolar transistor turn-on effect in SOI CMOS ULSI. For a quarter-micron n-channel SOI MOSFET, results suggest a maximum power supply of 1.8 V. In the deep submicron regime, SOI devices exhibited a negative differential resistance due to increased self-heating with drain bias voltage. Detailed comparison with bulk devices suggested significant reduction in the drain-source avalanche breakdown voltage due to increased carrier injection at the source-body junction.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>