ESD performance of 65 nm partially depleted n and p channel SOI MOSFETs

Abstract

A study on the electrostatic discharge (ESD) behaviors of silicide blocked (Sblk) n and p channel MOSFETs is presented for a state-of-the-art 65nm SOI technology. It is observed that the charge in the floating body SOI MOSFETs helps to improve their ESD characteristics over the grounded body devices. The ESD behavior of the thin-oxide pMOSFETs shows failure current similar to the corresponding nMOSFETs but at the expense of higher power dissipation and higher parasitic bipolar transistor (pBJT) turn-on voltages. The study of gate-silicided (GS) and gate-non-silicided (GNS) nMOSFETs show that the GNS devices exhibit approximately 30% higher failure current than the similar sized GS devices. Transmission line pulsing (TLP) measurement with different stress pulse widths reveals that the self-heating effects are more pronounced in the GNS devices than the similar sized GS devices. The analytical thermal model for the bulk MOSFET when applied to the SOI MOSFET indicates that the high temperature region during the breakdown is not only at the drain-body junction but extends into the highly resistive drain silicide-blocked region.