Transistor Stuck-open Research Articles

Testing Ternary Content Addressable Memories With Comparison Faults Using March-Like Tests

Ternary content addressable memory (TCAM) plays an important role in various applications for its fast lookup operation. This paper proposes several comparison fault models (i.e., the faults cause Compare operation fail) of TCAMs based on electrical defects, such as shorts between two circuit nodes and transistor stuck-open and stuck-on faults. Two March-like tests for detecting comparison faults are also proposed. The first March-like test requires 4N Write operations, 3N Erase operations, and 4N+2B Compare operations to cover 100% of targeted comparison faults for an NtimesB-bit TCAM with Hit output only. The second March-like test requires 2N Write operations, 2N Erase operations, and 4N+2B Compare operations to cover 100% of targeted comparison faults for an NtimesB-bit TCAM with Hit and Priority Address Encoder outputs. Compared with the previous work, the proposed tests have lower time complexity for typical TCAMs; they can be used to test TCAMs with different comparator structures; and their time complexities are independent of the number of stuck-on faults. Also, they can cover delay faults in comparison circuits

Testable Designs of Multiple Precharged Domino Circuits

Domino CMOS circuits are an option for speeding up critical units. An inherent problem of Domino logic is that under specific input conditions the charge redistribution between parasitic capacitances at internal nodes of a circuit can violate the noise margins and cause erroneous responses at the output. The dominant solution to this problem is the multiple precharging of the gate's internal nodes. However, the added precharge transistors are not testable for stuck-open faults. Undetectable stuck-open faults at these transistors may cause noise margins reduction and consequently may affect the reliability of the circuit since its operation in the field will be sensitive to environmental factors such as noise. In this paper, we propose new multiple precharging design schemes that enhance Domino circuits' testability with respect to transistor stuck-open and stuck-on faults

New efficient totally self-checking Berger code checkers

This paper presents a new method for designing totally self-checking (TSC) Berger code checkers for any number k of information bits, even for k=2 r−1 , taking into account realistic faults as stuck-at, transistor stuck-open, transistor stuck-on and resistive bridging faults. Double- as well as single-output TSC checkers are given. The proposed single-output TSC Berger code checkers are the first in the open literature. The checkers designed following the proposed method are significantly more efficient, with respect to the required area and speed, than the corresponding already known from the open literature checkers.

Testable designs of one-count generators

Testable realizations of One-Count Generators (OCGs) with respect to an extended fault model, including the stuck-at, transistor stuck-open, and transistor stuck-on faults using current monitoring, are presented. These implementations are made up of testable components which are commonly found in current CMOS libraries. A new design method for OCGs is given which offers the ability to apply a desired robust pair of vectors at the inputs of every element of the OCG (and hence any desired single vector to them), as well as the ability to propagate the effect of any single fault to a primary output of the OCG.

Hierarchical robust test generation for CMOS circuit stuck-open faults

As VLSI circuits become very large the complexity of test derivation becomes tremendous. The performance of test derivation can be improved significantly by exploiting the hierarchical structure found in most realistic circuits and supported by current computer-aided design systems. In this direction, a new hierarchical test generation methodology for transistor stuck-open (TSOP) faults in combinational CMOS circuits, is presented. The contribution of this work is twofold. For the designer of the CMOS cells we give a method, based on the Karnaugh map, to generate the sufficient test information for the CMOS cells, and for the designer of a VLSI circuit consisting of these CMOS cells we give a method to generate robust two-pattern tests for the whole VLSI circuit exploiting the test information given for any one of the used CMOS cells.

Design of stuck-open fault testable CMOS complex gates

Tests that detect transistor stuck-open (TSOP) faults independent of timing skews in input changes may not exist for all TSOP faults in CMOS complex gates. A new design method is presented which does not require any extra hardware or test inputs to improve the testability of a CMOS complex gate.

Robust test generation for transistor stuck-open faults in CMOS complex gates

In this paper we give a new, systematic method to generate robust two-pattern test sets for transistor stuck-open (TSOP) faults in CMOS complex gates, using the Karnaugh map under a new approach. We consider CMOS complex gates consisting of transistor networks of either the sum of products (SP) or the products of sum (PS) forms. Following the proposed method, all the unteslable TSOP faults are easily identified and the corresponding networks can be redesigned in order to become robustly testable. Our method is so simple and straightforward that it can be applied easily and quickly even in a manual processing way.

Testable design of BiCMOS circuits for stuck-open fault detection using single patterns

Single BJT BiCMOS devices exhibit sequential behavior under transistor stuck-OPEN (s-OPEN) faults. In addition to the sequential behavior, delay faults are also present. Detection of s-OPEN faults exhibiting sequential behavior needs two-pattern or multipattern sequences, and delay faults are all the more difficult to detect. A new design for testability scheme is presented that uses only two extra transistors to improve the circuit testability regardless of timing skews/delays, glitches, or charge sharing among internal nodes. With this design, only a single vector is required to test for a fault instead of the two-pattern or multipattern sequences. The testable design scheme presented also avoids the requirement of generating tests for delay faults. >

SWiTEST: a switch level test generation system for CMOS combinational circuits

Switch level test generation (SLTG) is potentially more powerful than conventional gate level test generation (GLTG) or CMOS circuits. Over the last decade much research has been carried out on SLTG. However to date no widely accepted SLTG system exists. The objectives of this work are to analyze the various problems associated with SLTG, to identify a feasible way to deal with these problems, and to develop an efficient and useful SLTG system for combinational circuits. The basic idea is to make use of as many GLTG concepts as possible without modeling a CMOS circuit at the gate level. Based on the analysis of CMOS circuits and faults, a SLTG system called SWiTEST has been developed. This system can deal with bridging, transistor stuck-open, transistor stuck-on and stuck-at faults. It employs both logic and current (IDDQ testing) monitoring and takes into account the invalidation problem associated with stuck-open tests. The framework of this system is PODEM-based. To be applicable to switch level circuits, the basic PODEM algorithm has been enhanced to deal with concepts such as multiple objective selection, search-based backtracing and incremental event-driven logic implication. Experimental results indicate that SWiTEST is quite efficient in both CPU time and memory usage. >

Analysis and Design of Regular Structures for Robust Dynamic Fault Testability

Recent methods of synthesizing logic that is fully and robustly testable for dynamic faults, namely path delay, transistor stuck-open and gate delay faults, rely almost exclusively on flattening given logic expressions into sum-of-products form, minimizing the cover to obtain a fully dynamic-fault testable two-level representation of the functions, and performing structural transformations to resynthesize the circuit into a multilevel network, while also maintaining full dynamic-fault testability. While this technique will work well for random or control logic, it is not practical for many regular structures.To deal with the synthesis of regular structures for dynamic-fault testability, we present a method that involves the development of a library of cells for these regular structures such that the cells are all fully path-delay-fault, transistor stuck-open fault or gate-delay-fault testable. These cells can then be utilized whenever one of these standard functions is encountered.We analyze various regular structures such as adders, arithmetic logic units, comparators, multipliers, and parity generators to determine if they are testable for dynamic faults, or how they can be modified to be testable for dynamic faults while still maintaining good area and performance characteristics. In addition to minimizing the area and delay, another key consideration is to get designs which can be scaled to an arbitrary number of bits while still maintaining complete testability. In each case, the emphasis is on obtaining circuits which are fully path-delay-fault testable. In the process of design modification to produce fully robustly testable structures, we have derived a number of new composition rules that allow cascading individual modules while maintaining robust testability under dynamic fault models.

Testing for floating gate faults in CMOS combinational circuits

Multiple transistor stuck-open and -short faults in CMOS combinational circuits may develop into a situation where the ordered pair of test vectors (initializer, sensitizer) is not effective in detecting such faults. These faults cause the output line of the basic CMOS logic gate to be in a floating state. Hence, the output line cannot be appropriately initialized for testing. These faults are called ‘floating gate faults’. An analysis of the effects of such faults on CMOS combinational circuits is presented. A procedure to identify such faults is outlined. The logic transistor function model is adopted, based on which a systematic test generation scheme to achieve an effective test is introduced.

Multiple stuck-at faults detection in CMOS combinational gates

The problem of designing easily testable CMOS combinational circuits is afforded. Two CMOS structured design techniques are presented. The novelty of this approach relies upon the complete fault detection of single and multiple line stuck-at, transistor stuck-open and stuck-on faults for combinational circuits. The test algorithm requires only minimal modifications to detect also a large number of bridging faults. The techniques are both based on the addition of two transistors, a P-FET and a N-FET, placed in series between the P and N sections. In the first case (Dynamic Fully CMOS - DFCMOS), they are controlled by a single input; in the other (Testable Fully CMOS - TFCMOS) there is one input for each additional transistor. The test procedure is defined and it is s shown that multiple faults detection can be easily achieved.

Fault simulation of unconventional faults in CMOS circuits

The authors present a novel technique to study the detection of non-stuck-at faults in CMOS circuits. Gate-level models of CMOS faults not yet adequately covered in the literature are developed. Suitable models for transistor stuck-open and stuck-on, gate-drain shorts, and bridgings are implemented in a fault simulator. Results obtained with typical circuits are presented and discussed to analyze the influence of circuit architecture and type of test vector (deterministic or pseudorandom) on the coverage of non-stuck-at faults. The following general conclusions are drawn from these results: (1) shorts between transistor gate and drain are adequately detected by stuck-at oriented test patterns, and, hence, they do not represent a significant problem in IC testing: (2) the coverage of transistors stuck-open is significantly dependent on the test pattern generation method used; (3) the detectability of bridgings depends strongly on the circuit topology; and (4) the indirect coverage of transistors stuck-on is inadequate, essentially because a large number of them are undetectable. >

Design for testability techniques for CMOS combinational gates

The design of easily testable CMOS combinational circuits is discussed. Two CMOS structured design techniques are presented. The novelty of this approach is the complete fault detection of single- and multiple-line stuck-at, transistor stuck-open, and stuck-on faults for combinational circuits. The test algorithm requires only minimal modifications to detect a large number of bridging faults. These techniques are both based on the addition of two transistors, a P-FET and an N-FET, which are placed in series between the P and N sections. In the first case (dynamic fully CMOS, DFCMOS), the transistors are controlled by a single input; in the other case (testable fully CMOS, TFCMOS), there is one input for each additional transistor. The test procedure is presented, and it is shown that multiple fault detection can be easily achieved. >

Testability strategy and test pattern generation for register files and customized memories

A testability strategy is presented for registers and memories embedded in multiprocessor chips as designed with the Cathedral-II/2nd silicon compilation environment. The implementation requires the design of a scan register, which is able to maintain a value at its output while scanning a vector into the scan chain. A test algorithm for the register file, based on the concept of C-testability, is derived. The fault model covers both stuck-at and most transistor stuck-open and stuck-closed cases. Large embedded memories customized to particular purposes are important in highly multiplexed processor systems. Therefore, a test strategy with wide fault coverage, for single- and double-buffered random access and pointer-addressed memories has been implemented with a self-test approach.

A testability strategy for microprocessor architecture

The authors present a method for fully testing chips designed using synthesis and silicon compilation. The method is targeted for a multiprocessor architecture that implements low-speed to medium-speed signal-processing algorithms. By taking advantage of the specific properties of the architecture, the method allows a chip to be partitioned into several functional units. The authors use the C-test concept instead of the traditional automatic test-pattern generation to derive a compact set of test vectors. The fault model covers both the stuck-at class and part of the transistor stuck-open and stuck-closed cases. For large units with embedded memory, the authors adopt a self-test approach.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

MOS Test Pattern Generation Using Path Algebras

There is extensive evidence that the classical, stuck-at fault model, operating at the gate level, is inadequate for testing MOS VLSI circuits. By contrast, a ``nonclassical,'' switch-level model?directly representing open and short circuits in the interconnect and transistors stuck-open or stuck-on?allows important effects such as MOSFET bidirectionality and tristate behavior to be taken into account. This paper describes a new switch-level method for generating the singular cover of an MOS primitive gate using path algebras. The method yields tests to cover all specified interconnect open and short circuits, and all irredundant transistor stuck-open and stuck-on faults, should such tests exist. It relies on specification of an appropriate algebra by redefinition of the operators used in computing powers of a matrix. Two such algebras are required?one to generate tests for open circuit faults and the other for short circuit faults. Test generation for networks of primitive gates is achieved in two stages: after deriving singular covers for the primitives, a variant of the D-algorithm with modified ``D-drive'' is used. The approach is unified and powerful, having the potential to detect parasitic latch behavior and to generate tests for any of the current MOS VLSI technologies. In common with most present automatic test generation methods, it is restricted to combinational logic. Practical limits on the size of circuit which can be dealt with appear comparable to those set by use of the classical D-algorithm.