Multiple stuck-at faults detection in CMOS combinational gates

Abstract

The problem of designing easily testable CMOS combinational circuits is afforded. Two CMOS structured design techniques are presented. The novelty of this approach relies upon the complete fault detection of single and multiple line stuck-at, transistor stuck-open and stuck-on faults for combinational circuits. The test algorithm requires only minimal modifications to detect also a large number of bridging faults. The techniques are both based on the addition of two transistors, a P-FET and a N-FET, placed in series between the P and N sections. In the first case (Dynamic Fully CMOS - DFCMOS), they are controlled by a single input; in the other (Testable Fully CMOS - TFCMOS) there is one input for each additional transistor. The test procedure is defined and it is s shown that multiple faults detection can be easily achieved.