Testing for floating gate faults in CMOS combinational circuits

Abstract

Multiple transistor stuck-open and -short faults in CMOS combinational circuits may develop into a situation where the ordered pair of test vectors (initializer, sensitizer) is not effective in detecting such faults. These faults cause the output line of the basic CMOS logic gate to be in a floating state. Hence, the output line cannot be appropriately initialized for testing. These faults are called ‘floating gate faults’. An analysis of the effects of such faults on CMOS combinational circuits is presented. A procedure to identify such faults is outlined. The logic transistor function model is adopted, based on which a systematic test generation scheme to achieve an effective test is introduced.