Transistor Structures Research Articles

Single silicon synaptic device for stochastic binary spike-timing-dependent plasticity

In this paper, we present a single silicon synaptic device that enables stochastic binary spike-timing-dependent plasticity. The single silicon synaptic device, which is similar to a conventional metal-oxide-semiconductor field-effect transistor structure, is implemented using standard complementary metal-oxide-semiconductor technology. The stochastic nature of the feedback mechanism induced by weak impact ionization is experimentally demonstrated. Because of probabilistic dynamics in the feedback mechanism, the single silicon synaptic device features stochastic binary spike-timing-dependent plasticity.

Complementary Doped Source-Based Reconfigurable Schottky Diode as an Equivalence Logic Gate.

A complementary doped source-based reconfigurable Schottky diode (CDS-RSD) is proposed for the first time. Unlike other types of reconfigurable devices that have source and drain (S/D) regions with the same material, this has a complementary doped source region as well as a metal silicide drain region. Compared to three-terminal reconfigurable transistors, which have both the program gate and control gate, the proposed CDS-RSD does not have a control gate but only a program gate for reconfiguration operation. The drain electrode of the CDS-RSD is not only the output terminal of the current signal but also the input terminal of the voltage signal. Therefore, it is a reconfigurable diode based on high Schottky barriers for both the conduction band and valence band of silicon, which formed on the interface between the silicon and drain electrode. Therefore, the CDS-RSD can be regarded as the simplification of the reconfigurable field effect transistor structure on the premise of retaining the reconfigurable function. The simplified CDS-RSD is more suitable for the improvement of logic gate circuit integration. A brief manufacture process is also proposed. The device performance has been verified through device simulation. The performance of the CDS-RSD as a single-device two-input equivalence logic gate has also been investigated.

AlGaN HEMT Structures Grown on Miscut Si(111) Wafers.

A complex study was performed on a set of AlGaN/GaN high-electron-mobility transistor structures grown by metalorganic vapor phase epitaxy on miscut Si(111) wafers with a highly resistive epitaxial Si layer to investigate the influence of substrate miscut on their properties. The results showed that wafer misorientation had an influence on the strain evolution during the growth and surface morphology, and could have a strong impact on the mobility of 2D electron gas, with a weak optimum at 0.5° miscut angle. A numerical analysis revealed that the interface roughness was a main parameter responsible for the variation in electron mobility.

P‐6: Study of source‐gated transistor (SGT) for output current enhancement through TCAD simulation

Source‐gated transistor (SGT) proves to be a promising candidate as an alternative structure for displays. However, the on‐current of SGT is relatively low when compared with conventional thin‐film transistor structures. This research proposes a new structure with higher current while retaining SGT characteristics. This structure is suitable for low power and wearable devices.

32‐2: Mask Reducing Backplane Architecture for Advanced Micro‐LED Display

In this work, a novel thin film transistor (TFT) structure named ASD was prepared, which means active layer bottom‐contact with source/drain(SD) layer. ASD device use the first light shield metal layer served as SD electrode simultaneously, which can reduce 2‐count‐mask array process compared with traditional top gate (TG) device. The mobility and subthreshold swing of the ASD a‐IGZO TFT device can reach 14 cm2/Vs and 0.18 V/dec, respectively. The PBTS and NBTIS are within 0.5V through process optimization. In addition, a 7.1 inch Micro‐LED display used ASD TFT backplane has demonstrated, and Finally, the Micro‐LED panel shows +0.7V Vth shift after the high temperature and high humidity operation (HTHHO) 500h reliability test.

APPLICATION OF SILICON CARBIDE SAND IN THE TECHNOLOGY OF PROCESSING THE REVERSE SIDE OF SILICON TRANSISTOR STRUCTURES

A method is proposed for processing the reverse side of silicon transistor structures before the metal deposition process and obtaining contact to the collector of the transistor being formed. The parameters of the surface roughness of the silicon surface treated with carbide–silicon sand are studied in order to improve the adhesive properties before spraying the contact to the collector region of the transistor.

Fabrication of Low On‐Resistance and Normally Off AlGaN/GaN Metal Oxide Semiconductor Heterojunction Field‐Effect Transistors with AlGaN Back Barrier by the Selective Area Regrowth Technique

Herein, a recessed‐gate AlGaN/GaN metal oxide semiconductor heterojunction field‐effect transistor (MOS‐HFET) with an AlGaN back‐barrier layer fabricated by a selective area regrowth (SAG) technique is investigated. A recessed‐gate structure enables normally off operation required for power‐switching applications. A thin AlGaN/GaN channel and the AlGaN back‐barrier structures are fabricated on a Si substrate by metal–organic chemical vapor deposition. The 50 nm thick, thin GaN channel layer with a smooth surface is grown on the AlGaN back‐barrier layer. A recessed‐gate structure is successfully formed by SAG of an AlGaN/GaN layer on the thin AlGaN/GaN layer. The regrown AlGaN/GaN high electron mobility transistor structure shows lower sheet resistance owing to high concentration and high mobility of a two‐dimensional electron gas. Transfer characteristics of the thin AlGaN/GaN channel MOS‐HFETs show normally off operation as a consequence of using the AlGaN back‐barrier structure. Channel mobility becomes five times higher than that of GaN channel in the case of using the thin AlGaN/GaN channel. These results indicate that the regrown thin AlGaN/GaN channel MOS‐HFET has the potential to realize low on‐resistance and normally off operation.

Performance analysis of gallium nitride-based DH-HEMT with polarization-graded AlGaN back-barrier layer

In this paper, polarization-graded AlGaN back-barrier nanolayer has been introduced to improve the DC and RF parameters of gallium nitride-based high electron mobility transistors (HEMT). To explore the characteristics, both graded and non-graded double heterojunction high electron mobility transistor (DH-HEMT) structures are optimized using SILVACO-ATLAS physical simulator. Enhanced DC and RF parameters have been observed in the optimized graded DH-HEMT. In this paper, we have also studied the development of the quantum wells at the AlGaN/GaN interfaces due to the conduction band discontinuity in both structures.

Qualitative Analysis & Advancement of Asymmetric Recessed Gates with Dual Floating Material GaN HEMT for Quantum Electronics

The Impact of Aluminium nitride (AlN) Spacer, Gallium Nitride (GaN) Cap Layer, Front Pi Gate (FG) and Back Pi Gate(BG), High K dielectric material such as Hafnium dioxide(HfO2), Aluminium Oxide (Al2O3), Silicon nitride (Si3N4) on Aluminium Galium Nitride/ Gallium Nitride (AlGaN/GaN), Heterojunction High Electron Mobility Transistor (HEMT) of 6nm(nanometer) technology is simulated and extracted the results using the Silvaco Atlas TCAD tool. The importance of High K dielectric materials like Al2O3 and Si3N4 are studied for the proposal of GaN HEMT. AlN, GaN Cap Layers, and High K Dielectric material are layered one on another to overcome the conventional transistor draw backs like surface defects, scattering of the electron, and less mobility of electron. Hot electron effect is overcome by Pi type gate. Therefore, by optimizing the HEMT structure the abilities for certain devices are converted to abilities. The dependency on DC characteristics and RF characteristics due to GaN Cap Layers, Multi gate (FG &BG), and High K Dielectric material is established. Further Compared Single Gate (SG) Passivated HEMT, Double Gate (DG) Passivated HEMT, Double Gate Triple(DGT) Tooth Passivated HEMT, High K Dielectric Front Pi Gate (FG) and Back Pi Gate (BG) Nanowire HEMT. It is observed that there is an increased Drain Current (Ion) of 5.92(A/mm), low Leakage current(Ioff) 5.54E-13 (A) of Transconductance (Gm) of 3.71(S/mm), Drain Conductance (Gd) of 1.769(S/mm), Cutoff frequency(fT) of 743 GHz Maximum Oscillation frequency (Fmax) 765 GHz, Minimum Threshold Voltage (Vth) of -4.5V, On Resistance (Ron)of 0.40(Ohms) at Vgs =0V. These outstanding characteristics and transistor structure of proposed HEMT and materials involved to apply for upcoming generation High-speed GHz frequency applications.

P-type nickel oxide deposited by reactive hollow cathode gas flow sputtering for the potential usage in thin-film transistors

Thin Nickel Oxide film were deposited by reactive pulsed-direct current hollow cathode gas flow sputtering. This unique technique allows for sputtering magnetic target materials with very high rates without magnetron. Deposition was carried out from a nickel target at room temperature. The influence of process parameters on optical, electrical, and structural film properties are investigated. High deposition rates of 6 nm/s and 2 nm/s are achieved for both direct current and pulsed-direct current power supply. All films are highly resistive and show p-type conduction that is tunable with oxygen flow. The films exhibit optical band gap around 3,8 eV depending on process parameters like oxygen flow and pulsing parameter. Secondary electron microscopy shows pillar-like growth perpendicular to the surface, while grazing incidence X-ray diffraction reveals smaller, randomly oriented crystals. Electrical properties of the films were tested by Hall measurements, revealing mobilities in the range of 1 cm2Vs. The nano crystalline thin films were tested in staggered bottom gate Thin-Film Transistor structures for potential use as channel layer.

Simulation study on the influence of metal contact and MOS interface trap states on the electrical characteristics of SiC IGBT

A 13 kV class n-channel 4H–SiC trench gate insulated gate bipolar transistor (IGBT) structure is designed based on Silvaco TCAD device simulator tool. The influence of metal/SiC and SiC MOS interface trap states on the static and dynamic characteristics of SiC IGBT devices are systematically studied. It is found that the electrical properties of SiC IGBTs are insensitive to the donor or acceptor traps at the interface of metal/SiC and the donor traps at the SiC/SiO2 interface. However, the acceptor traps at the SiC/SiO2 interface affect the electrical properties of SiC IGBTs greatly. When the acceptor trap density at the SiC/SiO2 interface (Dita) is up to the level of 1012 cm−2·eV−1, the turn-on voltage drop (VCEON) is increased gradually with the augmentation of Dita. The breakdown voltage (VBR) of the device is increased slightly. Further study of the device’s turn-off characteristics shows that the turn-off loss (EOFF) is decreased with the increase in Dita but a large tail current is formed. The mechanism may be that when the electrons are injected from the N+ source region into the N− drift region, the SiC/SiO2 interfacial acceptor traps at the side wall of trench gate capture a large number of electrons. As a result, the minority carrier concentration is decreased, and the conductance modulation effect on the N− drift region is weakened.

VES-BJT: A Lateral Bipolar Transistor on SOI with Polysilicon Emitter and Collector

This paper summarizes the results of investigations of bipolar transistors made in VESTIC (Vertical Slit Transistor-based Integrated Circuits) technology. This technology was proposed by W. Maly as an alternative to classical bulk CMOS technology. However, the basic VESTIC cell can be used not only to make field effect transistors but also to make bipolar transistors. Their structures differ in many ways from existing structures of bipolar transistors. The investigations reported here aim to answer the question: can VESTIC-based lateral bipolar transistors be useful as active devices, and can they be made technologically compatible with field effect VESTIC devices? The theoretical studies were followed by the fabrication and measurements of VESTIC-based p-n-p and n-p-n bipolar devices. Although the manufacturing technology available was far from optimal, working bipolar devices were obtained. The results show that VESTIC-based bipolar devices may achieve acceptable parameters if made with state-of-the-art manufacturing technology. The main outcome of the research reported in the paper is that p-n-p and n-p-n bipolar transistors with acceptable parameters may be fabricated, together with field effect devices, in VESTIC-based integrated circuits. As a result, the VESTIC technology could become the new original BiCMOS technology.

Effects of GaN channel downscaling in AlGaN–GaN high electron mobility transistor structures grown on AlN bulk substrate

In this work, two series of AlGaN/GaN/AlN high electron mobility transistor (HEMT) heterostructures have been grown by molecular beam epitaxy on AlN bulk substrates. The effects of reduction in the GaN channel thickness as well as the AlGaN barrier thickness and composition on structural and electrical properties of the heterostructures have been studied. The material analysis involved high-resolution x-ray diffraction, atomic force microscopy, and cross-sectional transmission electron microscopy. In a first series of HEMT structures grown with an aluminum content of 30% in the AlGaN barrier, the channel downscaling results in a reduction in the GaN strain relaxation rate but at the expense of degradation in the mean crystal quality and in the electron mobility with a noticeable increase in the sheet resistance. An opposite trend is noticed for the three-terminal breakdown voltage of transistors, so that a trade-off is obtained for a 50 nm width GaN channel HEMT, which exhibits a sheet resistance of 1700 Ω/sq. with transistors demonstrating three-terminal breakdown voltage up to 1400 V for 40 μm gate to drain spacing with static on resistance Ron = 32 mΩ cm2. On the other hand, a second series of HEMT structures with high aluminum content AlGaN barriers and sub-10 nm GaN channels have been grown perfectly strained with high sheet carrier densities allowing to preserve sheet resistances in the range of 880–1050 Ω/sq.

Electron Transport Properties in High Electron Mobility Transistor Structures Improved by V-Pit Formation on the AlGaN/GaN Interface

This work suggests new morphology for the AlGaN/GaN interface which enhances electron mobility in two-dimensional electron gas (2DEG) of high-electron mobility transistor (HEMT) structures. The widely used technology for the preparation of GaN channels in AlGaN/GaN HEMT transistors is growth at a high temperature of around 1000 °C in an H2 atmosphere. The main reason for these conditions is the aim to prepare an atomically flat epitaxial surface for the AlGaN/GaN interface and to achieve a layer with the lowest possible carbon concentration. In this work, we show that a smooth AlGaN/GaN interface is not necessary for high electron mobility in 2DEG. Surprisingly, when the high-temperature GaN channel layer is replaced by the layer grown at a temperature of 870 °C in an N2 atmosphere using TEGa as a precursor, the electron Hall mobility increases significantly. This unexpected behavior can be explained by a spatial separation of electrons by V-pits from the regions surrounding dislocation which contain increased concentration of point defects and impurities.

Non-volatile logic-in-memory ternary content addressable memory circuit with floating gate field effect transistor

Due to the limitations of the currently widely used von Neumann architecture-based computing system, research on various devices and circuit systems suitable for logic-in-memory computing applications has been conducted. In this work, the silicon-based floating gate memory cell transistor structure, which has been attracting attention as a memory to replace the dynamic random access memory or NAND Flash technology, was newly recalled, and its applicability to logic-in-memory application was confirmed. This floating gate field effect transistor (FGFET) has the advantage that the compatibility of the existing silicon-based complementary metal–oxide–semiconductor (CMOS) process is far superior to that of logic-in-memory application devices to which materials with new memory characteristics are applied. At the 32 nm technology node, which is the front node to which the planar MOSFET structure is applied, an analysis environment that can simultaneously analyze the device and circuit of the FGFET was established. For a seamless connection between FGFET-based devices and circuit analysis, the compact model of the FGFET was developed, which is applied to logic-in-memory ternary content addressable memory (TCAM) circuit design. It was verified that the two types of logic-in-memory TCAM circuits to which FGFETs are applied are superior to a conventional CMOS FET-based TCAM circuit in the number of devices used (=circuit area) and power/energy efficiency.

SELF-OSCILLATING PARAMETRIC HUMIDITY SENSOR WITH FREQUENCY OUTPUT SIGNAL

A self-oscillating parametric humidity sensor has been developed that implements the principle of "humidity-frequency" conversion into hybrid integrated circuit based on a microelectronic transistor structure with a negative differential resistance, in which the humidity-sensitive element is a resistor of the HR202 type. For the purposes of determining parameters self-oscillating parametric humidity sensor with frequency output a mathematical model has been developed that takes into account the effect of humidity on a sensitive resistive element, which is an integral element of the device. Based on the mathematical model, analytical expressions for the transformation function and the sensitivity equation are obtained. It is shown that the main contribution to the conversion function is made by relative humidity. The computer simulation and experimental studies of a self-oscillating parametric humidity sensor with a frequency output signal contributed to obtaining the main parameters and characteristics, such as the dependence of the generation frequency on changes in relative humidity in the range from 30% to 99%, the change in sensitivity on relative humidity, the dependence of the active and reactive components of the impedance in the frequency range from 50 kHz to 2 GHz; standing wave ratio, change in logarithmic magnitude and spectra of the output signal of a parametric humidity sensor with a frequency output signal in the LTE-800 Downlink frequency range. The obtained electrical characteristics confirm the operability of the developed device. The sensitivity of the developed self-oscillating parametric humidity sensor in the range of relative humidity change from 30% to 99% has a value from 332.8 kHz/% to 130.2 kHz/%.

The impact of multi-layered dielectrics on the electrical performance of ZnO thin-film transistors

The electrical performance of ZnO thin film transistors (TFTs) fabricated on three different dielectric layers is investigated using an inverted staggered bottom gate thin film transistor structure. This work demonstrated the potential of integrating high-k dielectrics in ZnO TFTs in a dielectric multi-layered stack using SiO2 as the support layer for all the hero-dielectrics layers. In order to achieve this, ZnO thin film semiconducting layers were deposited at room temperature by radio frequency (RF) sputtering method and with no post deposition heat treatment, making them suitable candidates for low cost large area electronics on low temperature substrates (such as plastics). The dielectric films investigated were aluminium nitride (AlN), silicon nitride (SiN) and silicon dioxide (SiO2). The effective mobility of SiN devices was about half that observed in AlN devices. However, the dielectric layers exhibited hysteresis of approximately 0 V, 2 V and 7 V for the SiO2, AlN and SiN respectively. In addition, SiO2 TFTs have lowest threshold voltage (VT) and turn-on voltage (Von). The capacitance-voltage measurement for these device show that the flatband and threshold voltage of SiN and AlN MOS capacitors shifted towards more negative voltages instead when compared with the single layer SiO2 devices.

Three-Dimensional MoS2 Nanosheet Structures: CVD Synthesis, Characterization, and Electrical Properties

The proposed study demonstrates a single-step CVD method for synthesizing three-dimensional vertical MoS2 nanosheets. The postulated synthesizing approach employs a temperature ramp with a continuous N2 gas flow during the deposition process. The distinctive signals of MoS2 were revealed via Raman spectroscopy study, and the substantial frequency difference in the characteristic signals supported the bulk nature of the synthesized material. Additionally, XRD measurements sustained the material’s crystallinity and its 2H-MoS2 nature. The FIB cross-sectional analysis provided information on the origin and evolution of the vertical MoS2 structures and their growth mechanisms. The strain energy produced by the compression between MoS2 islands is assumed to primarily drive the formation of vertical MoS2 nanosheets. In addition, vertical MoS2 structures that emerge from micro fissures (cracks) on individual MoS2 islands were observed and examined. For the evaluation of electrical properties, field-effect transistor structures were fabricated on the synthesized material employing standard semiconductor technology. The lateral back-gated field-effect transistors fabricated on the synthesized material showed an n-type behavior with field-effect mobility of 1.46 cm2 V−1 s−1 and an estimated carrier concentration of 4.5 × 1012 cm−2. Furthermore, the effects of a back-gate voltage bias and channel dimensions on the hysteresis effect of FET devices were investigated and quantified.

Carrier Transport Properties in Few-Layer WS0.3Se1.7/(WOx)WS0.3Se1.7 Lateral p+–n Junctions Using a Metal–Oxide–Semiconductor Field-Effect Transistor (MOSFET) Structure

The carrier transport properties of lateral p+–n junctions composed of few-layer WS0.3Se1.7/(WOx)WS0.3Se1.7 on thermally grown SiO2 or high-κ amorphous Al0.74Ti0.26Oy dielectric layers on p+-Si substrates were investigated and analyzed using field-effect transistor structures. Plasma-laser irradiation promoted selective oxidation near the few-layer WS0.3Se1.7 surface and improved the rectification behavior of the current–voltage characteristics. A photocurrent current density (Jph) of 4 × 10–7 A/cm2 was recorded for WS0.3Se1.7/(WOx)WS0.3Se1.7 lateral p+–n junctions under simulated solar-light (AM1.5G) irradiation. Subsequently, improved Jph values of 7.1 × 10–6 (∼17 times) and 1.23 × 10–5 A/cm2 (∼30 times) were obtained by inserting a silver (Ag) back-reflector layer between the amorphous Al0.74Ti0.26Oy dielectric layer and p+-Si and an adding an antireflection (AR) layer of SnO2, respectively. In addition, an enhanced Jph of 1.3 × 10–5 A/cm2 was achieved with a Voc of 0.84 V and an FF of 57% upon applying a gate bias of +12 V. Thus, the photonic and electronic design of lateral p+–n junctions composed of few-layer WS0.3Se1.7/(WOx)WS0.3Se1.7 structures contributes to further research on various types of 2D lateral heterostructures for the application in optoelectronic and photovoltaic devices.

Single-Electron Transport and Detection of Graphene Quantum Dots

The integrated structure of graphene single-electron transistor and nanostrip electrometer was prepared using the semiconductor fabrication process. Through the electrical performance test of the large sample number, qualified devices were selected from low-yield samples, which exhibited an obvious Coulomb blockade effect. The results show that the device can deplete the electrons in the quantum dot structure at low temperatures, thus, accurately controlling the number of electrons captured by the quantum dot. At the same time, the nanostrip electrometer coupled with the quantum dot can be used to detect the quantum dot signal, that is, the change in the number of electrons in the quantum dot, because of its quantized conductivity characteristics.