Transistor Scaling Research Articles

Precise p-type and n-type doping of two-dimensional semiconductors for monolithic integrated circuits

The controllable fabrication of patterned p-type and n-type channels with precise doping control presents a significant challenge, impeding the realization of complementary metal-oxide-semiconductor (CMOS) logic using a single van der Waals material. However, such an achievement could offer substantial benefits by enabling continued transistor scaling and unprecedented interlayer interconnect technologies. In this study, we devise a precise method for two-dimensional (2D) semiconductor substitutional doping, which allows for the production of wafer-scale 2H-MoTe2 thin films with specific p-type or n-type doping. Notably, we extend this approach to the synthesis of spatially selective doped 2H-MoTe2 thin films via a one-step growth method, facilitating the monolithic integration of p-type and n-type semiconductor channels. Leveraging this advancement, we successfully fabricate a chip-sized 2D CMOS inverter array that demonstrates excellent device performance and yield. Collectively, these findings represent a significant stride towards the practical incorporation of 2D semiconductors in very large-scale integration technology.

Improved Thermal Dissipation in a MoS2 Field-Effect Transistor by Hybrid High-k Dielectric Layers.

Transition metal dichalcogenides like MoS2 have been considered as crucial channel materials beyond silicon to continuously advance transistor scaling down owing to their two-dimensional structure and exceptional electrical properties. However, the undesirable interface morphology and vibrational phonon frequency mismatch between MoS2 and the dielectric layer induce low thermal boundary conductance, resulting in overheating issues and impeding electrical performance improvement in the MoS2 field-effect transistors. Here, we employed hybrid high-k dielectric layers of Al2O3/HfO2 to simultaneously reduce the interfacial thermal resistance and improve device electrical performance. The enhanced contact, greater vibrational phonon overlapping region, and stronger interfacial bonding force between the top Al2O3 layer and MoS2 promote the heat removal efficiency across the interface to the substrate. Under the same input power density, the temperature profile of the MoS2 transistor on the Al2O3/HfO2 has been largely reduced compared to that of the device on HfO2, with a maximum reduction of 49.5 °C. In addition, the field-effect mobility and current of MoS2 devices on the Al2O3/HfO2 high-k dielectric layers have been significantly improved, attributed to the depressed electron scattering and trap states at the interface. The design of the hybrid high-k dielectric layers provides an efficient solution to simultaneously improve the thermal and electrical performance of the two-dimensional devices.

Selecting alternative metals for advanced interconnects

Interconnect resistance and reliability have emerged as critical factors limiting the performance of advanced CMOS circuits. With the slowdown of transistor scaling, interconnect scaling has become the primary driver of continued circuit miniaturization. The associated scaling challenges for interconnects are expected to further intensify in future CMOS technology nodes. As interconnect dimensions approach the 10 nm scale, the limitations of conventional Cu dual-damascene metallization are becoming increasingly difficult to overcome, spurring over a decade of focused research into alternative metallization schemes. The selection of alternative metals is a highly complex process, requiring consideration of multiple criteria, including resistivity at reduced dimensions, reliability, thermal performance, process technology readiness, and sustainability. This Tutorial introduces the fundamental criteria for benchmarking and selecting alternative metals and reviews the current state of the art in this field. It covers materials nearing adoption in high-volume manufacturing, materials currently under active research, and potential future directions for fundamental study. While early alternatives to Cu metallization have recently been introduced in commercial CMOS devices, the search for the optimal interconnect metal remains ongoing.

Reliable Synchronous and Asynchronous Counter Design in QCA

Due to rapid growth in the integrated circuit (IC) industry, the demand for compact digital system design is high. However, the continued technology reductions made the feasibility of further scaling down transistor size more challenging. In response to the growing demand for ultra-compact IC designs, the revolutionary quantum-dot cellular automata (QCA) technology has emerged as a promising solution. In a digital era, the counters are widely adopted in the peer-to-peer process flow to establish a mechanism for generating unique values for each identifier/number. In this work, a unique synchronous and asynchronous counters architecture is proposed with a reliable D and T flip-flop design. The proposed QCA architecture is implemented and validated with the QCA designer tool. Furthermore, in QCA technology, unreliable QCA designs can lead to frequent errors and malfunctions in the implemented logic. To overcome this challenge, the proposed design prioritizes cell placement (the relative positions of QCA cells) to make the circuit more robust. As a result, the circuit can still produce the expected functionality even if some QCA cells malfunction. Hence, to ensure the reliability of the proposed QCA architecture, the missing cell defect analysis is carried out in comparison with existing state-of-the-art designs. Based on comparison results, the unique designs like the proposed multiplexer, D flip-flop and T flip-flop design exhibit success rates of 67.28, 77.04 and 85.15%, respectively. The experimental results demonstrate that the proposed counter-architecture outperforms existing architectures.

Research of Gate-All-Around Field-Effect Transistors

This report provides an overview of GAA FETs also known as Gate-All-Around FETs, focusing on their introduction and limitations, based on a comprehensive review of current literature and online resources. GAA FETs represent an evolution of FinFET technology, which itself was developed from traditional MOSFET designs. Each iteration has aimed to improve performance and overcome limitations of its predecessor. The GAA architecture offers superior electrostatic control, resulting in higher drive currents, reduced leakage, and improved subthreshold swing, making it ideal for high-performance, low-power applications. Despite these advantages, GAA FETs still face challenges with short-channel effects (SCEs) as device dimensions shrink. Gate-All-Around (GAA) is a transistor architecture designed to address the limitations of the FinFET design. Unlike FinFET, where the channel is surrounded on three sides by the gate, GAA surrounds the channel on all four sides by turning the FinFET structure sideways, making the channels horizontal. This design provides enhanced control over the transistor switch. The fabrication of GAA transistors involves a series of highly precise processes, which enable improved transistor scaling with reduced variability, resulting in increased performance and lower power consumption.

Efficient quantum-dot adder optimisation and analysis for future circuits

ABSTRACT In recent years, the rapid scaling of transistors has necessitated the exploration of advanced alternatives to Complementary metal oxide semiconductor(CMOS) technology for future progress. Quantum-dot cellular automata(QCA) technology has emerged as a promising solution, offering highly dense, high-speed, and low-power circuits. Among the critical digital building blocks, adder circuits play a crucial role in arithmetic and logic units. Consequently, optimising these circuits in terms of area, delay, and quantum cost is essential for the development of efficient designs. This paper presents effective multi-layer n-bit ripple carry adder(RCA) circuits, utilising full adder(FA) circuit. The outputs are generated in distinct layers and verified using the QCADesigner-Ev2.2 tool with bi-stable and coherence vector energy setups, employing Euler and Runge-Kutta methods.Additionally, the proposed designs are evaluated for various design metrics at three different scale factors(1,0.8889,and 0.7778), corresponding to cell sizes of 18 × 18 nm , 16 × 16 nm , and 14 × 14 nm respectively. The temperature’s impact on the average output polarisation of the FA is explored. The research demonstrates an n-bit-RCA surpassing existing designs with cost optimisations of 89.5%, 86%, and 90.3% for 4-bit,8-bit and 16-bit circuits, respectively. The paper also provides a thorough energy dissipation analysis for the proposed adder design.

Scaling of N-Type Field-Effect Transistors Based on Aligned Carbon Nanotube Arrays.

Wafer-scale aligned carbon nanotubes (A-CNTs) are promising candidate semiconductors for building high-performance complementary metal-oxide-semiconductor (CMOS) transistors for future integrated circuits (ICs). A-CNT-based p-type field-effect transistors (P-FETs) have demonstrated excellent performance and scalability down to sub-10 nm nodes. However, the development of A-CNT n-type FETs (N-FETs) lags far behind, in regard to their electronic performance and device scaling. In this work, we fabricated top-gated N-FETs based on A-CNTs with a scandium (Sc)-contacted source and drain. High-performance A-CNT N-FETs were demonstrated with record on-state current (Ion) exceeding 1 mA/μm and peak transconductance (gm) of 0.4 mS/μm. Interestingly, the A-CNT N-FETs exhibited abnormal scaling behavior owing to the lateral oxidation of low-work function source/drain contacts, leading to formidable challenges to scale both the gate length (Lg) and the contact length (Lc) at the same time. Understanding of the abnormal scaling behavior contributes to seeking solutions for high-performance A-CNT N-FETs, and it paves the way for future CNT CMOS digital IC technology.

Two-Dimensional Semiconductors for State-of-the-Art Complementary Field-Effect Transistors and Integrated Circuits.

As the trajectory of transistor scaling defined by Moore's law encounters challenges, the paradigm of ever-evolving integrated circuit technology shifts to explore unconventional materials and architectures to sustain progress. Two-dimensional (2D) semiconductors, characterized by their atomic-scale thickness and exceptional electronic properties, have emerged as a beacon of promise in this quest for the continued advancement of field-effect transistor (FET) technology. The energy-efficient complementary circuit integration necessitates strategic engineering of both n-channel and p-channel 2D FETs to achieve symmetrical high performance. This intricate process mandates the realization of demanding device characteristics, including low contact resistance, precisely controlled doping schemes, high mobility, and seamless incorporation of high- κ dielectrics. Furthermore, the uniform growth of wafer-scale 2D film is imperative to mitigate defect density, minimize device-to-device variation, and establish pristine interfaces within the integrated circuits. This review examines the latest breakthroughs with a focus on the preparation of 2D channel materials and device engineering in advanced FET structures. It also extensively summarizes critical aspects such as the scalability and compatibility of 2D FET devices with existing manufacturing technologies, elucidating the synergistic relationships crucial for realizing efficient and high-performance 2D FETs. These findings extend to potential integrated circuit applications in diverse functionalities.

An energy and information analysis method of logic gates based on stochastic thermodynamics.

To reduce the energy consumption of logic gates in digital circuits, the size of transistors approaches the mesoscopic scale, e.g. sub-7 nanometers. However, existing energy consumption analysis methods exhibit various deviation for logic gates when the nonequilibrium information processing of mesoscopic scale transistors with ultra-low voltages is analyzed. Based on the stochastic thermodynamics theory, an information energy ratio method is proposed for the energy consumption estimation of XOR gates composed of mesoscopic scale transistors. The proposed method provides a new insight to quantify the transformation between the information capacity and energy consumption for XOR gates and extending to other logic gates. Utilizing the proposed analysis method, the supply voltage of the parity check circuit can be optimized by numerical simulations without expensive and complex practical measurements. The information energy ratio is the first analytical method to quantify the energy and information transformation of logic gates at the mesoscopic scale.

Simulation of Novel Nano Low-Dimensional FETs at the Scaling Limit.

The scaling of bulk Si-based transistors has reached its limits, while novel architectures such as FinFETs and GAAFETs face challenges in sub-10 nm nodes due to complex fabrication processes and severe drain-induced barrier lowering (DIBL) effects. An effective strategy to avoid short-channel effects (SCEs) is the integration of low-dimensional materials into novel device architectures, leveraging the coupling between multiple gates to achieve efficient electrostatic control of the channel. We employed TCAD simulations to model multi-gate FETs based on various dimensional systems and comprehensively investigated electric fields, potentials, current densities, and electron densities within the devices. Through continuous parameter scaling and extracting the sub-threshold swing (SS) and DIBL from the electrical outputs, we offered optimal MoS2 layer numbers and single-walled carbon nanotube (SWCNT) diameters, as well as designed structures for multi-gate FETs based on monolayer MoS2, identifying dual-gate transistors as suitable for high-speed switching applications. Comparing the switching performance of two device types at the same node revealed CNT's advantages as a channel material in mitigating SCEs at sub-3 nm nodes. We validated the performance enhancement of 2D materials in the novel device architecture and reduced the complexity of the related experimental processes. Consequently, our research provides crucial insights for designing next-generation high-performance transistors based on low-dimensional materials at the scaling limit.

(Invited) Material Engineering for the GAA and Post-GAA Transistors and Interconnects

Feature scaling in advanced CMOS technology has been slowing down starting at 10 nm node and is expected to stop completely in the next few years. Nevertheless, transistor density scaling is continuing at a Moore’s law pace, driven by DTCO and 3D IC.Transistor dimensions and minimum metal pitch are expected to be massaged down only by 10% to 20% during the next decade. However, both the transistor and the interconnect will continue to evolve and improve both in performance and in variability.Currently, the industry is transitioning from FinFET technology to GAA (Gate All-Around) technology. The next transition, from GAA to the NMOS and PMOS GAA transistors stacked on top of each other (often referred to as CFET (Complementary Field Effect Transistor)) is expected in 8 to 10 years from now.The main methodology for GAA and CFET transistor engineering comes down to bandstructure engineering, where material composition, shape and thickness of different layers, and mechanical stress are engineered to tailor a bandstructure of the channel that maximizes on-state driving strength and minimizes off-state leakage and variability. The key methodology for bandstructure engineering is ab-initio analysis of transistor components and then transfer of the obtained bandstructure to transistor scale analysis to characterize its behavior.For the interconnect engineering, the tight metal pitches and increasingly tall and narrow vias dictate transition from copper to alternative metals, with a preference for the metals that can be etched and selectively grown. The key methodology for interconnect engineering is ab-initio analysis of electron scattering at the interfaces and grain boundaries. The scattering is then converted into interconnect resistance that defines speed and power consumption of the advanced CMOS circuits.This work introduces the concepts of transistor band structure engineering and interconnect scattering engineering and provides illustrations of these methodologies applied to GAA and post-GAA technologies.

All-2D-Materials Subthreshold-Free Field-Effect Transistor with Near-Ideal Switching Slope.

The Boltzmann Tyranny, set by thermionic statistics, dictates the lower limit of switching slope (SS) of a MOSFET to be 60 mV/dec, the fundamental barrier for low-dissipative electronics. The large SS leads to nonscalable voltage, significant leakage, and power consumption, particularly at short channels, making transistor scaling an intimidating challenge. In recent decades, an array of steep-slope transistors has been proposed; none is close to an ideal switch with ultimately abrupt switching (SS ∼ 0 mV/dec) between the binary logic states. We demonstrated an all-2D-materials van-der-Waals-heterostructure (vdW)-based FET that exhibits ultrasteep switching (0.33 mV/dec), a large on/off current ratio (∼107), and an ultralow off current (∼0.1 pA). The "Subthreshold-Free" operation achieved by the collective behavior of functional materials enables FET switching directly from the OFF-state to the ON-state with entirely eliminated subthreshold region, behaving as the ideal logic switch. Two-inch wafer-scale device fabrication is demonstrated. Boosted by device innovation and emerging materials, the research presents an advancement in achieving the "beyond-Boltzmann" transistors, overcoming one of the CMOS electronics' most infamous technology barriers that have plagued the research community for decades.

Circuits implementations using carbon nanotube field-effect transistor nanotechnology

Device scaling is a pivotal aspect in the field of electronics, aimed at enhancing the performance of integrated circuits (ICs) by reducing the dimensions of transistors. The device scaling presents the short channel effects (SCEs) in the nanoscale regime. To address the SCEs, nanometer IC designers have turned to the carbon nanotube field-effect transistor (CNTFET) technology, which offers unique properties and mitigates the challenges associated with transistor scaling. In this research work, a leakage reduction technique known as the input-dependent (INDEP) method is suggested to tackle the leakage current issue at the nanoscale regime using CNTFET technology. The INDEP method involves the incorporation of two additional transistors within the logic circuit. To evaluate the efficacy of the INDEP method, a CNTFET-based 7-stage inverter chain is meticulously designed at 32 nm CNTFET technology node. Subsequent comparative analysis against alternative designs is conducted, assessing performance metrics such as power dissipation, delay, and power delay product (PDP). The suggested INDEP method reduces power dissipation by 83.75% and improves PDP by 78.44%. Furthermore, the study delves into the impact of process, voltage, and temperature (PVT) variations. Additionally, the investigation explores the influence of parameters such as the number of carbon nanotubes, temperature, supply voltage, and chiral indices on the performance of the 7-stage inverter chain. The simulation results demonstrate that the CNTFET-based INDEP technique yields promising outcomes, characterized by low power dissipation, precise output, and minimal uncertainty across all evaluated metrics.

Approximate Computing Based Low-Power FPGA Design for Big Data Analytics in Cloud Environments

As cloud computing continues to evolve, the demand for scalable and energy-efficient infrastructure to handle extensive applications becomes paramount. Traditional transistor scaling and microprocessor design methods no longer suffice to meet the growing scale of cloud usage. This research explores the potential of approximate computing (AC) as an innovative solution to these challenges, particularly in high-demand computational settings. AC, known for its ability to make controlled accuracy trade-offs, is identified as a key strategy for improving both the performance and energy efficiency of cloud infrastructure, with a focus on low-power Field-Programmable Gate Array (FPGA) designs. This paper introduces novel methodologies that harness the strengths of AC, emphasizing its application in neural-based and machine-learning techniques for energy-efficient solutions. By targeting the performance of AC, especially in varied application domains and complex data mining scenarios, we propose two groundbreaking approaches that significantly enhance computational speed and reduce energy consumption. Our empirical analysis demonstrates notable improvements over existing techniques, highlighting the effectiveness of AC in optimizing cloud infrastructure. The proposed model on FPGA through cloud computing attains substantial elevation rates by 89 % and energy reduction by 122%, which had been good outcomes. This study not only confirms the benefits of integrating AC with low-power FPGA designs for cloud environments but also sets a new benchmark for future research in achieving more sustainable and efficient cloud computing via VLSI FGPA design analysis solutions.

Simulation of 2D ReS2/WSe2 based complementary field-effect transistors towards 1 nm technology node

Advanced Integrated Circuit technology demands high-performance channel materials and innovative device architectures to sustain the scaling of field-effect transistors. In this study, we simulate the electrical performance of rhenium disulfide and tungsten diselenide nanosheet FETs (NSFETs) with gate lengths ranging from 12 nm to 8 nm using Technology Computer-Aided Design method. The simulated high performance including 393 μA/μm on-state current and over 105 on/off ratio can meet the criteria for integrated circuit applications in the 1 nm technology node. Complementary FET (CFET) simulations are conducted through the vertical stacking of ReS2 and WSe2 NSFETs, exhibiting a small parasitic capacitance of 1.0 fF/μm, and notable noise margin (>235 mV) at different process corners. The construction and performance simulation of Static Random-Access Memory (SRAM) is realized through CFET interconnection, involving the calculation of read current and read/write noise margin. This research offers a forward-looking analysis of performance metrics for future 2D materials-based NSFETs, CFETs, and SRAMs.

CVD graphene contacts for lateral heterostructure MoS2 field effect transistors

Intensive research has been carried out on two-dimensional materials, in particular molybdenum disulfide, towards high-performance field effect transistors for integrated circuits1. Fabricating transistors with ohmic contacts is a challenging task due to the formation of a high Schottky barrier that severely limits the performance of the transistors for real-world applications. Graphene-based heterostructures can be used in addition to, or as a substitute for unsuitable metals. In this paper, we present lateral heterostructure transistors made of scalable chemical vapor-deposited molybdenum disulfide and chemical vapor-deposited graphene achieving a low contact resistances of about 9 kΩ·µm and high on/off current ratios of 108. Furthermore, we also present a theoretical model calibrated on our experiments showing further potential for scaling transistors and contact areas into the few nanometers range and the possibility of a substantial performance enhancement by means of layer optimizations that would make transistors promising for use in future logic integrated circuits.

Impact of channel thickness on device scaling in vertical InGaZnO channel charge-trap memory transistors with ALD Al2O3 tunneling layer

This study investigates the impact of channel thickness (TCH) variation on memory performance and its physical origins in vertical channel charge trap memory (V-CTM) using InGaZnO (IGZO) channels for X–Y scaling. When the TCH decreased, the subthreshold slope (SS) increased from 0.21 to 0.30 V/dec, while the minimum program voltage decreased from 12 to 8 V, indicating a performance trade-off. The analysis of bulk trap density extracted by SS, density of states distribution, and x-ray photoelectron spectroscopy confirmed an increase in the number of trap states and hydrogen-related defects in the IGZO channel when a thin TCH is employed. As a result, it was expected that the barrier height at the active layer/TL would be lowered during program operations at relatively thin channel. However, the SS would also be degraded due to an increase in sub-gap states, such as OH- and VOH, induced by hydrogen incorporation. The V-CTM with an optimal TCH of 7 nm had a maximum memory window of 5.7 V. The program/erase states were maintained for 106 s before experiencing a 50 % charge loss, and 5-level memory states were verified to be available within a memory window of 3.2 V for 108 s with little degradation. It was noteworthy that the long-term reliability and multilevel implementation could be secured for the V-CTM with a TCH as thin as 7 nm, demonstrating the sound feasibility of its X–Y scaling. This work presents new key parameters and understanding of device integration issues for future 3D structured memory transistors, and aims to contribute to the advancement of memory technologies using oxide semiconductor channels.

Integrated 2D multi-fin field-effect transistors

Vertical semiconducting fins integrated with high-κ oxide dielectrics have been at the centre of the key device architecture that has promoted advanced transistor scaling during the last decades. Single-fin channels based on two-dimensional (2D) semiconductors are expected to offer unique advantages in achieving sub-1 nm fin-width and atomically flat interfaces, resulting in superior performance and potentially high-density integration. However, multi-fin structures integrated with high-κ dielectrics are commonly required to achieve higher electrical performance and integration density. Here we report a ledge-guided epitaxy strategy for growing high-density, mono-oriented 2D Bi2O2Se fin arrays that can be used to fabricate integrated 2D multi-fin field-effect transistors. Aligned substrate steps enabled precise control of both nucleation sites and orientation of 2D fin arrays. Multi-channel 2D fin field-effect transistors based on epitaxially integrated 2D Bi2O2Se/Bi2SeO5 fin-oxide heterostructures were fabricated, exhibiting an on/off current ratio greater than 106, high on-state current, low off-state current, and high durability. 2D multi-fin channel arrays integrated with high-κ oxide dielectrics offer a strategy to improve the device performance and integration density in ultrascaled 2D electronics.

Novel crosstalk circuit design for high density logic applications

As IC transistors scale down further, physical limitations are restricting performance growth. The contradiction between demands for computing capabilities and challenges in transistor downscaling is exacerbating. This paper proposed a crosstalk circuit design using interconnect coupling capacitance to improve the computing power of chips. Firstly, a valid model of coupling capacitance between metal interconnects is established based on analysis of the factors affecting coupling capacitance. Then, basic crosstalk gates including NAND and NOR are designed by adopting line crosstalk and sampling inverters. Furthermore, complex logic gates and combination circuits are implemented by using the basic crosstalk gates. For verification, a test chip based on line computing is fabricated in 65 nm CMOS technology and the core area is ∼0.019 mm2. The experimental results verified the correctness of the proposed crosstalk gate's logic. Compared with standard logic circuit, the crosstalk NAND or NOR gates reduce the area overhead by 10.6 % and also enhance the circuit's capability of anti-reverse engineering.

CNT thin films based on epoxy mixtures: fabrication, electrical characteristics

The simple scaling of silicon transistors no longer ensures the advantages of high energy efficiency, driving research into nanotechnologies beyond silicon. Specifically, digital circuits based on carbon nanotube (CNT) field-effect transistors promise significant advantages in energy efficiency. However, the inability to perfectly control internal nanoscale defects and the variability of carbon nanotubes hinder the realization of very large-scale integrated systems. In this study, we investigated a novel method for fabricating transistors based on carbon nanotubes (CNTs) using epoxy mixtures, obtained the electrical properties of the transistors, and compared their microstructure and composition via the scanning electron microscopy. The carrier mobility on epoxy-based transistors was 28.87 cm²/V∙s, and the transistor switching frequency was 2.2 MHz. The samples exhibited electrical and physical stability over an extended period of time. The use of carbon nanotubes in epoxy resin as a conducting layer for transistors opens significant prospects in the field of electronics. The CNT-epoxy mixture technology allows for more flexible and rapid fabrication of thin-film transistors compared to classical methods. However, it is not appropriate to speak of a complete replacement; in this study, we present an alternative method for producing thin-film transistors, which may be of interest for specific purposes.