Noise In Transistors Research Articles

Strong Coulomb scattering effects on low frequency noise in monolayer WS2 field-effect transistors

When atomically thin semiconducting transition metal dichalcogenides are used as a channel material, they are inevitably exposed to supporting substrates. This situation can lead to masking of intrinsic properties by undesired extrinsic doping and/or additional conductance fluctuations from the largely distributed Coulomb impurities at the interface between the channel and the substrate. Here, we report low-frequency noise characteristics in monolayer WS2 field-effect transistors on silicon/silicon-oxide substrate. To mitigate the effect of extrinsic low-frequency noise sources, a nitrogen annealing was carried out to provide better interface quality and to suppress the channel access resistance. The carrier number fluctuation and the correlated mobility fluctuation (CNF-CMF) model was better than the sole CNF one to explain our low-frequency noise data, because of the strong Coulomb scattering effect on the effective mobility caused by carrier trapping/detrapping at oxide traps. The temperature-dependent field-effect mobility in the four-probe configuration and the Coulomb scattering parameters are presented to support this strong Coulomb scattering effect on carrier transport in monolayer WS2 field-effect transistor.

The noise performance of CMOS Miller operational transconductance amplifiers with embedded current‐buffer frequency compensation

SummaryThe noise of cascode transistors is usually considered to be negligible. It is demonstrated in this paper that this is not the case for an operational transconductance amplifiers exploiting Miller compensation via an embedded current buffer. Analysis, validated through simulations, shows that the noise power spectral density of the cascode transistor implementing the buffer, can be dominant at high frequencies. Its contribution can be of the same order of magnitude as that of the transistors in the first gain stage. A design equation is also given to limit the increase of this output noise contribution. Copyright © 2016 John Wiley & Sons, Ltd.

Low-Frequency Noise in Advanced SiGe:C HBTs—Part I: Analysis

In this paper, we present extensive characterization of low-frequency noise in advanced silicon germanium heterojunction bipolar transistors. We demonstrate the extraction methodology of base and collector noise spectral densities for a wide range of transistor geometries. In addition to 1/ $f$ noise, generation–recombination (G–R) mechanisms are observed at low bias in the base current noise. Their existence is confirmed by Random Telegraph Signal (RTS) noise measurements. 1/ $f$ and G–R components are extracted from the base current noise spectra and their bias dependencies are studied. Finally, base current noise spectral densities measured at the same base current density in different geometries are compared to study the individual contribution of 1/ $f$ noise from the periphery as well as the intrinsic device. Part II of this paper will discuss the modeling aspects and noise correlation.

A compact model for flicker noise in MOSFETs considering both correlated mobility and carrier number fluctuations

In this work, a consistent, physics-based, one-equation-all-regions model for flicker noise in MOS transistors that considers both mobility and carrier number fluctuations is presented. The final r...

Low-Frequency Noise in Gate Tunable Topological Insulator Nanowire Field Emission Transistor near the Dirac Point**Supported by the National Basic Research Program of China under Grant No 2012CB921703, the National Natural Science Foundation of China under Grant Nos 11174357 and 11574379, and the Strategic Priority Research Program of Chinese Academy of Sciences under Grant No XDB07010300.

Low-frequency flicker noise is usually associated with material defects or imperfection of fabrication procedure. Up to now, there is only very limited knowledge about flicker noise of the topological insulator, whose topologically protected conducting surface is theoretically immune to back scattering. To suppress the bulk conductivity we synthesize antimony doped Bi2Se3 nanowires and conduct transport measurements at cryogenic temperatures. The low-frequency current noise measurement shows that the noise amplitude at the high-drain current regime can be described by Hooge's empirical relationship, while the noise level is significantly lower than that predicted by Hooge's model near the Dirac point. Furthermore, different frequency responses of noise power spectrum density for specific drain currents at the low drain current regime indicate the complex origin of noise sources of topological insulator.

A CMOS low noise amplifier with employing noise cancellation and modified derivative superposition technique

A wide band resistive feedback CMOS low noise amplifier (LNA) with Modified Derivative Superposition (MDS) technique is designed by using TSMC RF CMOS 0.18μm technology. In this paper, the main NMOS transistor is biased in strong inversion and auxiliary NMOS transistor is biased in the moderate inversion, so third order nonlinear current of two transistors can be canceled out and high third order input intercept point (IIP3) can be attained. In other method, the main NMOS transistor is biased in moderate inversion and an auxiliary PMOS transistor is biased in weak inversion. By this technique, second and third order input intercept point (IIP2 and IIP3) are improved. With common gate transistor in cascode structure and auxiliary transistor, thermal noise of main transistor can be canceled. The linearized LNA demonstrates IIP2 and IIP3 average improvement of +17dB and +18dB with PMOS transistor rather than NMOS transistor in the frequency range of 3.1–10.6GHz. Maximum power gain of 22dB, minimum noise figure (NF) of 2.3dB with a power dissipation of 5.3mW (without buffer) are obtained under a 1.8V power supply in the frequency range of 5–10.6GHz. The chip area is 660µm×748µm.

Novel source follower transistor structure without lightly doped drain for high performance CMOS image sensor

To realize high-resolution pixels in the CMOS image sensor, it is necessary to reduce low-frequency noise, particularly random telegraph signal (RTS) noise of the source-follower transistor (SFT). To achieve less relative variation of drain noise current, ΔID/ID, a metal–oxide–semiconductor field-effect transistor structure without the lightly doped drain (LDD) for the SFT transistor is proposed. Then, a comparison of RTS noise characteristics between the proposed SFT structure without LDD and the conventional SFT structure with LDD was conducted. Although the RTS noise occurrence probability of the proposed SFT structure without LDD is somewhat greater than that of the conventional SFT structure with LDD, the amplitude of relative variation of drain noise current of the proposed SFT structure is significantly less than that of the conventional SFT. Despite changes in several factors in the proposed SFT, such as effective channel length, trap depth profile in gate oxide, and random dopant fluctuation (RDF), it is believed that the change of trap depth profile is a primary factor for the improved RTS characteristic. Therefore, the proposed SFT is highly desirable for the high-resolution CMOS image sensor.

Low-frequency noise characteristics in the MOSFETs processed in 65 nm technology**Project supported by the National Natural Science Foundation of China (Nos. 61574048, 61204112) and the Guangdong Natural Science Foundation (No. 2014A030313656).

Low-frequency noise behavior in the MOSFETs processed in 65 nm technology is investigated in this paper. Low-frequency noise for NMOS transistors agrees with McWhorter's theory (carrier number fluctuation), low-frequency noise in the sub-threshold regime agrees with McWhorter's theory for PMOS transistors while it agree with Hooge's theory (carrier mobility fluctuation) in the channel strong inversion regime. According to carrier number fluctuation model, the extracted trap densities near the interface between channel and gate oxide for NMOS and PMOS transistor are 3.94 × 1017 and 3.56 × 1018 cm−3/eV respectively. According to carrier mobility fluctuation model, the extracted average Hooge's parameters are 2.42 × 10−5 and 4 × 10−4. By consideration of BSIM compact model, it is shown that two noise parameters (NOIA and NOIB) can model the intrinsic channel noise. The extracted NOIA and NOIB are constants for PMOS and their values are equal to 3.94 × 1017 cm−3/eV and 9.31 × 10−4 V−1. But for NMOS, NOIA is also a constant while NOIB is inversely proportional to the effective gate voltage. The extracted NOIA and NOIB for NMOS are equal to 3.56 × 1018 cm−3/eV and 1.53 × 10−2 V−1. Good agreement between simulation and experimental results is achieved.

Plasmonic noise of field-effect transistors operating at terahertz frequencies

We analyze electronic noise in field-effect transistors associated with plasma waves in the terahertz frequency domain by using a numerical approach based on the coupled hydrodynamic and Poisson equations. The current and voltage noise spectra, calculated by means of the transfer impedance method, exhibit a series of peaks associated with two- and three-dimensional plasma resonances. The two-dimensional plasma peaks have been found to depend on the channel length including gated and ungated regions. Under asymmetric boundary conditions, electrical instabilities characterized by terahertz oscillations of the drain voltage and gate current can be reached at sufficiently high values of the total drain current. A resonant enhancement of the plasma peaks in the noise spectra has been found to be a precursor of the instability onset. Through a spatial analysis of the local contributions we have shown that the main contribution to the total noise at frequencies near the plasma resonance comes from the ungated n-region placed between the source and the gate contacts.

Time-dependent simulation of particle and displacement currents in THz graphene transistors

Although time-independent models provide very useful dynamical information with a reduced computational burden, going beyond the quasi-static approximation provides enriched information when dealing with terahertz (THz) frequencies. In this work, the THz noise of dual-gate graphene transistors with DC polarization is analyzed from a careful simulation of the time-dependent particle and displacement currents. From such currents, the power spectral density (PSD) of the total current fluctuations are computed at the source, drain and gate contacts. The role of the lateral dimensions of the transistors, the Klein tunneling and the positive–negative energy injection on the PSD are analyzed. Through the comparison of the PSD with and without band-to-band tunneling and graphene injection, it is shown that the unavoidable Klein tunneling and positive–negative energy injection in graphene structures imply an increment of noise without similar increment on the current, degrading the (either low or high frequency) signal-to-noise ratio. Finally, it is shown that the shorter the vertical height (in comparison with the length of the active region in the transport direction), the larger the maximum frequency of the PSD. As a byproduct of this result, an alternative strategy (without length scaling) to optimize the intrinsic cut-off frequency of graphene transistors is envisioned.

Total dose effects on the g–r noise of JFET transistors**Project supported by the National Natural Science Foundation of China (Nos. 61076101, 61204092) and the Fundamental Research Funds for the Central Universities (No. JB150412).

Silicon junction field effect transistors (JFETs) have been exposed to Co60 γ-rays to study radiation-induced effects on their dc characteristics and noise. The devices have been irradiated and measured at room temperature up to an accumulated 100 krad(Si) dose of γ radiation at a dose rate of 0.1 rad (Si)/s. During irradiation, the generation–recombination (g–r) noise increase has been observed while the dc characteristics of the transistors were kept unchanged. The increasing of the density of the same type point defects and their probability of trapping and detrapping carriers caused by irradiation have been used to explain the g–r noise amplitude increase, while the g–r noise characteristic frequency has only a slight change.

Reducing flicker noise in chemical vapor deposition graphene field-effect transistors

Single-layer graphene derived from chemical vapor deposition (CVD) holds promise for scalable radio frequency (RF) electronic applications. However, prevalent low-frequency flicker noise (1/f noise) in CVD graphene field-effect transistors is often up-converted to higher frequencies, thus limiting RF device performance. Here, we achieve an order of magnitude reduction in 1/f noise in field-effect transistors based on CVD graphene transferred onto silicon oxide substrates by utilizing a processing protocol that avoids aqueous chemistry after graphene transfer. Correspondingly, the normalized noise spectral density (10−7–10−8 μm2 Hz−1) and noise amplitude (4 × 10−8–10−7) in these devices are comparable to those of exfoliated and suspended graphene. We attribute the reduction in 1/f noise to a decrease in the contribution of fluctuations in the scattering cross-sections of carriers arising from dynamic redistribution of interfacial disorder.

Extraction of microwave FET noise wave temperatures by using a novel neural approach

Purpose – The purpose of this paper is the development of an efficient approach for extraction of the microwave FET noise wave temperatures. Design/methodology/approach – The proposed approach is based on an artificial neural network (ANN) trained to determine the noise wave temperatures from the given measured transistor noise parameters. Findings – The presented approach enables not only efficient, but also an accurate direct extraction of the noise wave temperatures. This is confirmed by the validation of the proposed approach that is done by comparison of the transistor noise parameters obtained using the extracted noise wave temperatures with the measured noise parameters. Originality/value – Application of ANN is a novel approach to extract the noise wave temperatures, which provides more efficient microwave FET noise wave modeling.

Ultra-Low-Power Cryogenic SiGe Low-Noise Amplifiers: Theory and Demonstration

Low-power cryogenic low-noise amplifiers (LNAs) are desired to ease the cooling requirements of ultra-sensitive cryogenically cooled instrumentation. In this paper, the tradeoff between power and noise performance in silicon–germanium LNAs is explored to study the possibility of operating these devices from low supply voltages. A new small-signal heterojunction bipolar transistor noise model applicable to both the forward-active and saturation regimes is developed from first principles. Experimental measurements of a device across a wide range of temperatures are then presented and the dependence of the noise parameters on collector–emitter voltage is described. This paper concludes with the demonstration of a high-gain 1.8–3.6-GHz cryogenic LNA achieving a noise temperature of 3.4–5 K while consuming just ${\hbox{290}}~\mu{\hbox{W}}$ when operating at 15-K physical temperature.

Wave approach for noise modeling of gallium nitride high electron‐mobility transistors

AbstractThe wave approach has appeared as a very efficient tool for modeling as well as for measurements of noise parameters of microwave transistors. Having in mind the attractiveness of transistors in gallium nitride technology in modern communication systems, where it is very important to keep the noise on a low level and, thus, to have accurate transistor noise models, in this paper, the wave approach is applied for the noise modeling of high electron‐mobility transistor in gallium nitride technology. The noise wave representation of the transistor intrinsic circuit noise is used, where the noise wave parameters are modeled by exploiting the artificial neural networks. The modeling results, compared with the measured data and with those obtained by the conventional noise equivalent circuit model, provide a verification of the developed model accuracy. Copyright © 2015 John Wiley & Sons, Ltd.

Low-Frequency Noise and Random Telegraph Noise on Near-Ballistic III-V MOSFETs

In this paper, we report the observation of random telegraph noise (RTN) in highly scaled InGaAs gate-all-around (GAA) MOSFETs fabricated by a top-down approach. RTN and low-frequency noise were systematically studied for devices with various gate dielectrics, channel lengths, and nanowire diameters. Mobility fluctuation is identified to be the source of 1/f noise. The 1/f noise was found to decrease as the channel length scaled down from 80 to 20 nm comparing with classical theory, indicating the near-ballistic transport in highly scaled InGaAs GAA MOSFET. Low-frequency noise in ballistic transistors is discussed theoretically.

Experimental Study of Random Telegraph Noise in Trigate Nanowire MOSFETs

Random telegraph noise (RTN) in trigate nanowire transistors (NW Tr.) is systematically studied with respect to the NW size dependence. Time to capture and emission, which is related to the characteristic of the traps, such as trap energy, is independent of NW size. On the other hand, noise amplitude increases as the NW size decreases showing the similar size dependence to the reported scaled planar Tr. In addition, RTN after hot-carrier injection (HCI) and negative bias stress (NBS) is studied. HCI and NBS induce additional carrier traps, which generate larger noise signals. Since the degradation by HCI or NBS is larger with narrower width, RTN after these stresses is found to be severer in the NW Tr.

Observation of reduced 1/f noise in graphene field effect transistors on boron nitride substrates

We have investigated the low frequency (f) flicker (also called 1/f) noise of single-layer graphene devices on h-BN (placed on SiO2/Si) along with those on SiO2/Si. We observe that the devices fabricated on h-BN have on average one order of magnitude lower noise amplitude compared with devices fabricated on SiO2/Si despite having comparable mobilities at room temperature. We associate this noise reduction to the lower densities of impurities and trap sites in h-BN than in SiO2. Furthermore, the gate voltage dependent noise amplitude shows a broad maximum at Dirac point for devices on h-BN, in contrast to the M-shaped behavior showing a minimum at Dirac point for devices on SiO2, consistent with the reduced charge inhomogeneity (puddles) for graphene on h-BN. This study demonstrates that the use of h-BN as a substrate or dielectric can be a simple and efficient noise reduction technique valuable for electronic applications of graphene and other nanomaterials.

Terahertz bolometric detection by thermal noise in graphene field effect transistor

Monolayer (MLG) and bilayer (BLG) graphene devices have been fabricated with integrated antennas and have been investigated for a wideband terahertz (THz) detection at room temperature (RT). The devices show opposite (metallic vs. semiconducting, respectively) temperature coefficients of their resistance, which enable us to achieve a reproducible THz response via bolometric heating. The bolometric nature of this response is inferred by determining the spectral density of the 1/f resistance noise exhibited by the devices, as a function of the incident THz power. With increasing power, the spectral density varies in the two devices in a manner that reflects the opposite signs of their resistance temperature coefficients. The bolometric response is furthermore confirmed for both devices by the variation of their Hooge parameter as a function of the THz power. Overall, these observations confirm the capacity of graphene devices for sensitive broadband THz detection near RT.

Correlated noise in bipolar transistors: Model implementation issues

A new orthogonalization scheme is suggested for implementing correlated noise of bipolar transistors. The scheme provides a necessary condition on the non-quasi-static (NQS) models that can be used to obtain an implementation-suitable correlated noise model. One of the solutions presented here corresponds to a single node realization not reported so far. The gm-factor is introduced in the noise analysis explaining the deviations of a former noise model from device simulations. The model is extended to include the collector space-charge-region induced noise by retaining the simplicity of the realization and preserving the model parameter count.