Noise In Transistors Research Articles

Low-Frequency Noise in SONOS-TFT With a Trigate Nanowire Structure Under Program/Erase Operation

This letter investigates low-frequency noise (LFN) in polycrystalline silicon thin-film transistor (TFT) nonvolatile memory (NVM) under Fowler-Nordheim tunneling program/erase (P/E) operation. The NVM utilizes a silicon-oxide-nitride-oxide-silicon (SONOS)-type structure with a trigate multiple nanowire (NW) channels. The difference in the flicker noise (1/f) level between a multiple-channel NW device and a standard single-channel device became smaller after P/E cycling. The observation can be explained by the quantity of grain-boundary traps introduced by higher electric field at the NW corner during the P/E cycle, subsequently increasing the LFN level in the multiple NW SONOS-TFT.

Optimum Reliability Sizing for Complementary Metal Oxide Semiconductor Gates

Introducing redundancy at the device-level has been proposed as the most effective way to improve reliability. With the remarkable reliability of the complementary metal oxide semiconductor (CMOS) transistors the semiconductor industry was able to fabricate, the research on device-level redundancy has reduced. However, the increasing sensitivity to noise and variations (due to the massive scaling) of the CMOS transistors has led to a revival of interest in device-level redundancy schemes during the last decade. In this paper, we introduce a novel transistor sizing method that can be used to significantly reduce the probability of failure of CMOS gates due to threshold voltage variations. The method has almost no impact on the occupied area. For a given reliability target, the proposed sizing method provides very large scale integration (VLSI) designers with several transistor sizing options which allow them to optimize the trade-off between reliability and the traditional power-area-delay design parameters. The simulation results reported in this paper will show that the proposed transistor sizing method can improve the reliabilities of classical INV, NAND-2, and NOR-2 CMOS gates by factors of more than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> , 10, and 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> respectively, while the area is increased by less than 50%.

Label-free detection of DNA hybridization using transistors based on CVD grown graphene

The high transconductance and low noise of graphene-based field-effect transistors based on large-area monolayer graphene produced by chemical vapor deposition are used for label-free electrical detection of DNA hybridization. The gate materials, buffer concentration and surface condition of graphene have been optimized to achieve the DNA detection sensitivity as low as 1pM (10−12M), which is more sensitive than the existing report based on few-layer graphene. The graphene films obtained using conventional PMMA-assisted transfer technique exhibits PMMA residues, which degrade the sensing performance of graphene. We have demonstrated that the sensing performance of the graphene samples prepared by gold-transfer is largely enhanced (by 125%).

Dual-band low-phase-noise LC-QVCO using series coupling and switched biasing techniques

An LC-tank quadrature voltage-controlled oscillator (QVCO) is proposed to achieve frequency-band reconfigurability and low phase noise. In this work, phase noise contributed by the 1/f noise of coupling transistors and tail transistors is noticeably reduced when series coupling and switched biasing techniques are simultaneously adopted. The proposed QVCO was implemented in 0.25-μm triple-well CMOS process for K-PCS and WCDMA bands. Measured results showed a phase noise of −117 dBc/Hz at an offset of 1 MHz and a phase-noise figure-of-merit of −172 dBc/Hz while consuming 8.13 mA from a 2-V power supply.

Electrical Characteristic Analysis Using Low-Frequency Noise in Low-Temperature Polysilicon Thin Film Transistors

This study carried out an electrical characteristic analysis using low-frequency noise (LFN) in top gate p-type low-temperature polysilicon thin film transistors (LTPS TFTs) with different active layer thicknesses between 40 nm and 80 nm. The transfer characteristic curves show that the 40-nm device has better electrical characteristics compared with the 80-nm device. The carrier number fluctuation, with and without correlated mobility fluctuation model in both devices, has modeled well the measured noise. On the other hand, the trap density and coulomb scattering in the 40-nm device are smaller compared with the 80-nm device. To confirm the effectiveness of the LFN noise analysis, the trap densities at a grain boundary are extracted using in both devices the similar methods of Proano et al. and Levinson et al. That is, coulomb scattering, caused by the trapped charges at or near the interface, has a greater effect on the device with inferior electrical properties. Based on the LFN and the quantitative analysis of the trap density at a grain boundary, the interface traps between the active layer and the gate insulator can explain the devices' electrical degradation.

A quantum mechanical treatment of low frequency noise in high-K NMOS transistors with ultra-thin gate dielectrics

Our paper presents a quantum mechanical treatment of low-frequency noise in scaled NMOS transistors to extend the “unified” noise model and includes remote Coulomb scattering and surface roughness – the latter is a new consideration in the theory. Our experimental work focuses on scaled NMOS devices with a composite dielectric consisting of a 0.5nm SiO2 covered with a high-K, 1.6nm HfO2 with a metal gate. In the past, Coulomb scattering was assumed to arise from trapping centers located at the Si–SiO2 interface; however, this cannot give rise to a 1/f noise spectrum. We model remote Coulomb scattering into the dielectric film as traps in these films easily lie within a tunneling distance from the interface. This approach explains the decrease in the Coulomb scattering parameter (α) as a function of gate voltage. In addition, we introduce surface roughness scattering through fluctuations in the normal electric field due to fluctuations in the free carrier density with a surface scattering parameter (β) proportional to the SPICE surface roughness parameter, θS. Good agreement is obtained between our model and experimental results for both IDS–VGS and the power spectral density, SId, characteristics in very strong inversion region where surface quantization of the 2D subbands is strong.

Cryogenic Self-Calibrating Noise Parameter Measurement System

A system for measuring the noise parameters of a device at cryogenic temperatures is described. The method includes the thermal calibration of a module consisting of a noise diode, a dispersive coupling network, a temperature sensor, heater, and a bias-tee. The magnitude and phase of the reflection coefficient presented by the module vary rapidly with frequency and the noise output of the module can be thermally calibrated by changing the temperature of the module with an internal heater. The resulting variable impedance-calibrated noise source can be used to measure noise parameters of transistors or amplifiers over a frequency range of 0.4 to 12 GHz via the wideband frequency-variation method. The calibration scheme is not unique to the module and may be applied in general to any noise source. Calibration and noise parameter measurements are made at cryogenic temperatures on a discrete transistor and two different low-noise amplifiers. The results are compared against theoretical values and those obtained using independent measurements. To the best of the authors' knowledge, this is the first measurement of a transistor's noise parameters at cryogenic temperatures using such techniques.

Bias Dependant Noise Wave Modelling Procedure of Microwave Fets

Bias Dependant Noise Wave Modelling Procedure of Microwave Fets A new noise modelling procedure of microwave field-effect transistors (FETs) valid for various bias conditions is suggested in this paper. The proposed procedure is based on transistor noise wave model. With the aim to improve the noise wave model accuracy, the modification of the model is done by inclusion of the error correction functions into the noise wave model equations. It leads to significant reduction of deviations between measured and simulated noise parameters and therefore better noise prediction is achieved. It is also shown that once determined error correction functions can be applied for accurate noise modelling of the same device for various bias conditions. The validity of the presented noise modelling approach is exemplified by modelling of a specific MESFET device in packaged form.

A New Approach to Implementing High-Frequency Correlated Noise for Bipolar Transistor Compact Modeling

A new approach to implementing correlated high-frequency noise in bipolar junction transistor (BJT) large-signal compact models is developed by placing an RC -delayed noise current between the base and collector nodes. The approach reproduces the two stages of noise transport in a BJT, i.e., noise generation in the base and emitter and transportation through the collector-base junction space-charge region (CB SCR). The frequency dependence of the intrinsic noise sources due to the CB SCR is fully described with an accuracy value up to the second order of ω. As an example, the negative frequency dependence of Sic is correctly described for the first time. The approach is applicable to any large-signal compact model, and it is demonstrated using measurement data in both InGaP/GaAs heterojunction bipolar transistors (HBTs) and SiGe HBTs.

Experimental characterization of temperature‐dependent electron transport in single‐wall multi‐tube carbon nanotube transistors

AbstractCurrent–voltage, radio‐frequency (RF) and noise characteristics of single‐wall multi‐tube carbon nanotube (CNT) transistors were measured at cryogenic temperatures. Compared to an ambient temperature (Ta) of 300 K, only a slight drain current increase at Ta = 77 K was observed. In addition, a weak dependence of the maximum value of the current gain cut‐off frequency (fT) on Ta was obtained, indicating that fT is rather limited by the device intrinsic quantum and extrinsic capacitances than by an improved mobility due to reduced optical phonon scattering at low Ta. A noise analysis of the devices at Ta = 10 K reveals that the noise factor (NF) improvement at very low temperatures is related to the reduced Nyquist noise of all resistive transistor noise contributors. Since the main noise source in CNTFETs is the shot noise, NF remains comparatively high even at Ta = 10 K.magnified imagePhoto of the CNTFET embedded in RF pads (left) and schematic layout of the CNTFET (right).(© 2012 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

Wide-tuning-range, low-phase-noise quadrature ring oscillator exploiting a novel noise canceling technique

This paper presents a novel noise-canceling technique, which is used to improve the phase noise of a two-stage quadrature ring oscillator. The thermal noise canceling circuitry is used to cancel the channel thermal noise of the output transistors in each stage of the oscillator. Simulations using TSMC 0.13μm CMOS technology show a wide frequency tuning range of 315MHz to 6.64GHz and −97.5dBc/Hz at 1MHz offset from 4.7GHz for changing supply from 0.5V to 1.6V. The power consumption is obtained to be 14.8mW. The proposed oscillator can be used in applications such as ultra-wideband systems, and multiband and multimode receivers.

Mobility-Dependent Low-Frequency Noise in Graphene Field-Effect Transistors

We have investigated the low-frequency 1/f noise of both suspended and on-substrate graphene field-effect transistors and its dependence on gate voltage, in the temperature range between 300 and 30 K. We have found that the noise amplitude away from the Dirac point can be described by a generalized Hooge's relation in which the Hooge parameter α(H) is not constant but decreases monotonically with the device's mobility, with a universal dependence that is sample and temperature independent. The value of α(H) is also affected by the dynamics of disorder, which is not reflected in the DC transport characteristics and varies with sample and temperature. We attribute the diverse behavior of gate voltage dependence of the noise amplitude to the relative contributions from various scattering mechanisms, and to potential fluctuations near the Dirac point caused by charge carrier inhomogeneity. The higher carrier mobility of suspended graphene devices accounts for values of 1/f noise significantly lower than those observed in on-substrate graphene devices and most traditional electronic materials.

Low-Frequency Noise Study of p-Channel Bulk MuGFETs

The low-frequency (LF) noise in p-channel bulk Multiple-Gate Field-Effect Transistors (MuGFETs) with 2.5 nm SiON gate oxide has been investigated in the ohmic regime from weak to strong inversion. It is shown that both 1/f-like noise and Generation-Recombination (GR) noise are present, giving rise to a wide device-to-device scatter in the spectral density. The 1/f noise is dominated by number fluctuations from which an effective trap density in the range 5×1017 cm-3eV-1 has been derived. At the same time, it is demonstrated that the GR noise originates from traps in the gate oxide.

Measurement, analysis, and modeling of 1/f noise in pentacene thin film transistors

In order to facilitate accurate noise modeling of organic thin-film-transistors (OTFTs), we provide comprehensive experimental results and analysis of unique low frequency noise characteristics in OTFTs. We conduct drain current noise measurements for pentacene-based thin-film-transistors (TFTs) having different grain size and operating region and use the resulting data to provide detailed mechanistic understanding of the underlying noise-generation phenomena that exist in OTFTs. The results show carrier trapping by traps within the semiconductor is the dominant source of low frequency noise and can be used in conjunction with a conventional unified noise model to accurately describe the noise behavior of pentacene TFTs.

Origin of Low-Frequency Noise in the Low Drain Current Range of Bottom-Gate Amorphous IGZO Thin-Film Transistors

The low-frequency noise of bottom-gate amorphous IGZO thin-film transistors is investigated in the low drain current range. The noise spectra show generation-recombination (g-r) noise at drain currents <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> <; 5 nA, attributed to bulk traps located in a thin layer of the IGZO close to the conducting channel. At higher drain currents, a pure 1/ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> noise is observed. It is shown that the carrier number fluctuations are responsible for the 1/ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> noise due to trapping/detrapping of carriers in slow oxide traps, located near the interface with uniform spatial distribution.

Characterization of Low-Frequency Noise in GaAs Nanowire Field-Effect Transistors Controlled by Schottky Wrap Gate

Low-frequency noise in GaAs-based nanowire field-effect transistors (FETs) controlled by a Schottky wrap gate (WPG) is investigated focusing on the size dependence of 1/f noise and the basic behavior of a gentle slope of the noise spectrum at a relatively high frequency. 1/f noise is found to systematically depend on the nanowire width W and gate length LG, which is explained by the conventional flicker noise model. The evaluated flicker noise coefficient KF is on the order of 10-23 V2 F, comparable to that of Si metal–oxide–semiconductor (MOS) FETs. The gentle slope close to 1/f0.5 frequently appears in the noise spectrum from the fabricated devices. Its intensity is found to be proportional to gate leakage current, suggesting that electrons flowing through the AlGaAs barrier layer induce generation-recombination (GR) noise in the gate region.

Study of Gate Oxide/Channel Interface Properties of SON MOSFETs by Random Telegraph Signal and Low Frequency Noise

The aim of this paper is the investigation of the gate stack properties of submicron MOSFETs integrated in silicon on nothing technology and the identification of traps responsible for the current fluctuations by random telegraph signal (RTS) technique and low frequency technique. We show that the analysis of devices having random discrete fluctuations in the drain current, the analysis of the RTS noise parameters (amplitude, high and low state durations, activation energy, capture cross section) as a function of bias voltage and temperature, allows us to characterize the traps located in the interface (HfO2-SiO2)/Si. The conventional technique consists of statistical treatment of the RTS time-domain data. The study of RTS noise in submicron SON MOS transistors offers the opportunity of studying the trapping/detrapping behavior of a single interface trap. Furthermore, it has convincingly been shown that this discrete switching of the drain current between a high and a low state is the basic feature responsible for l/fγ flicker noise in MOSFETs transistors.

Low-frequency noise in junctionless multigate transistors

Low-frequency noise in n-type junctionless multigate transistors was investigated. It can be well understood with the carrier number fluctuations whereas the conduction is mainly limited by the bulk expecting Hooge mobility fluctuations. The trapping/release of charge carriers is related not only to the oxide-semiconductor interface but also to the depleted channel. The volume trap density is in the range of 6–30×1016 cm−3 eV−1, which is similar to Si–SiO2 bulk transistors and remarkably lower than in high-k transistors. These results show that the noise in nanowire devices might be affected by additional trapping centers.

LOW-FREQUENCY ELECTRONIC NOISE IN GRAPHENE TRANSISTORS: COMPARISON WITH CARBON NANOTUBES

We report results of the experimental investigation of the low-frequency noise in graphene transistors. The graphene devices were measured in three-terminal configuration. The measurements revealed low flicker noise levels with the normalized noise spectral density close to 1/f (f is the frequency) and the Hooge parameter αH ~10-3. Both top-gate and back-gate devices were studied. The analysis of the noise spectral-density dependence on the gate biases helped us to elucidate the noise sources in these devices. We compared the noise performance of graphene devices with that of carbon nanotube devices. It was determined that graphene devices works better than carbon nanotube devices in terms of the low-frequency noise. The obtained results are important for graphene electronic, communication and sensor applications.

Random telegraph-signal noise in junctionless transistors

Random telegraph-signal noise (RTN) is measured in junctionless metal-oxide-silicon field-effect transistors (JL MOSFETs) as a function of gate and drain voltage and temperature. It is shown that the RTN in JL MOSFETs increases significantly when an accumulation layer is formed. The amplitude of RTN is considerably smaller in JL devices than in inversion-mode MOSFET fabricated using similar fabrication parameters. A measurement technique is developed to extract the main parameters of the traps, including the average charge capture and emission time from the traps.