Transistor Logic Research Articles

Обзор логических базисов и микросхем при построении комбинационного устройства с учётом надёжности

The fundamental laws of the positive algebra of logic are considered, including the rules relating to the elements of equivalence and non-equivalence. Logic gates used in practice are presented. The whole set of standard schemes is implemented, in particular, the frontal version, minimized, in the "OR–NOT" basis, in the "AND–NOT" basis based on the initial logical dependence: ¬(¬(A¬B) × ¬(¬CD) + ¬(¬AB) × ¬(C¬D)) + ¬(¬(AB) × ¬(CD) + ¬(¬A¬B) × ¬(¬C¬D)) . A combination device based on K176LE5 chips has been designed. It is noted that the implementation of this function requires at least 3 chips in the Pier basis, which is not optimal in terms of reliability and weight and size indicators. The transition from the minimized variant to the basis of "Non-Equivalence" + "Conjunction", as well as the basis of "Equivalence" + "Pierce function" is carried out. The results of the search for existing chips that implement the functions "Exclusive OR", "AND", "Exclusive OR–NOT" and "OR-NOT" are presented. 4 groups of chips were found, such as: chips based on logic with emitter coupling (ECL), based on transistor-transistor logic (TTL), based on a series of CMOS chips: with a supply voltage of 5-15 V, and also with a supply voltage of 3-5 V. The corresponding descriptions of each of the MC10H1xx chips (group 1 series); K155xx, xx74xx (group 2 series); K561xx, CD40xxxx (group 3 series); SN74LVCxxx (group 4 series) are presented. Implementation options for these groups of chips in both bases are presented. The cost analysis of the applied microcircuits is made. The calculation of the final cost of products is presented. The conclusion is made about the expediency of using one or another group of microcircuits, depending on the initial requirements set.

A Novel Design of Full Adder Cell for VLSI Applications

The state-of-the-art digital integrated circuits (ICs) are becoming increasingly complex due to the increasing functionality along with high–performance and ultra-low power dissipation requirement. To meet the aforementioned requirement, a new low power and high performance 1-bit full adder cell is implemented based on gate diffusion input (GDI) and pass transistor logic (PTL) techniques. The delay, power, power delay product (PDP) and energy delay product (EDP) are extracted and compared for proposed full adder cell with other seven widely used full adders. The area is compared at 0.18 µm and 0.090 µm CMOS technology. The average power dissipation of proposed adder is 1.063 µW, C-CMOS is next higher value 1.377 µW and the NMNFA exhibits highest value 3.217 µW at a supply voltage of 1.2 V. The proposed adder reveals lower PDP (0.265 fJ) than the other adders. At all supply voltages proposed adder deliver low EDP value (0.070 fJ*nS) and it is minimum at 1.8 V because the delay is low at the same point which is dominating parameter in EDP. At supply voltage 1.2 V, the proposed adder exhibits improved performance EDP of 69.07% over the other best reported adder MBFA in this paper.

Design of Frequency Divider (FD/2 and FD 2/3) Circuits for a Phase Locked Loop

This paper reports on three design of Frequency Divider (FD/2) and Frequency Divider (FD 2/3) circuits. Tanner EDA tool developed on 130nm CMOS technology with a voltage supply of 1.3 V is used to build, model, and compare all circuits. For the FD/2 circuit, E-TSPC Pass Transistor logic uses 1.77 µW, whereas TSPC logic consumes 5.57 µW for the FD 2/3 circuit. It implies that the TSPC logic is the best solution since it meets the speed and power consumption requirements.

Bipolar Modulation of the Ionic Circuit for Generic Organic Photoelectrochemical Transistor Logic and Sensor

AbstractPhotonic (bio)electronic circuits and devices have been an enduring goal in modern photonics and electronics. Organic photoelectrochemical transistor (OPECT) interfacing light with biological world creates a substantial opportunity to this end due to the immense light−bio−matter interplay. Through modulating the invisible ionic circuit of organic electrochemical transistor (OECT) with a bipolar electrode (BPE) accommodating different semiconductor combinations, the unique photonic electronics toward logic and sensor applications are realized. Six combinations of BPEs are produced by the representative n‐type CdS/TiO2 and p‐type BiOI/NiO semiconductors, and the corresponding photonic characteristics and operation rationale are systematically investigated and explained. Designation of opto‐logic circuits and feasibility as a sensory platform are subsequently demonstrated. This work not only represents new photonic bioelectronics but also provides a generic mechanism for the design and development of advanced opto‐logics and bio‐analytics.

Reconfigurable Quasi-Nonvolatile Memory/Subthermionic FET Functions in Ferroelectric-2D Semiconductor vdW Architectures.

The functional reconfiguration of transistors and memory in homogenous ferroelectric devices offers significant opportunities for implementing the concepts of in-memory computing and logic-memory monolithic integration. Thus far, reconfiguration is realized through programmable doping profiles in the semiconductor channel using multiple-gate operation. This complex device architecture limits further scaling to match the overall chip requirements. Here, reconfigurable memory/transistor functionalities in a ferroelectric-gated van der Waals transistor by controlling the behavior of ferroelectric oxygen vacancies at the interface are demonstrated. Short- and long-term memory functions are demonstrated by modulating the border oxygen vacancy distribution and the associated charge dynamics. The quasi-nonvolatile long-term memory exhibits data retention of over 105 s and endurance of up to 5 × 105 cycles, verifying its applicability as a potential device platform for neuromorphic networks. More importantly, by modulating the ferroelectricity of the interfacial domains with the interactions of oxygen vacancies, a hysteresis-free logic transistor is realized with a subthermionic subthreshold swing down to 46mV dec-1 , which resembles a negative-capacitance field-effect transistor. The new concept of achieving functional reconfiguration with prior device performance in a single-gate ferroelectric field-effect transistor is of great advantage in future integrated circuit applications.

Use of Ambipolar Dual-Gate Carbon Nanotube Field-Effect Transistor to Configure Exclusive-OR Gate

As the physical scaling limit of silicon-based integrated circuits is approached, new materials and device structures become necessary. The exclusive-OR (XOR) gate is a basic logic gate performed as a building block for digital adder and encrypted circuits. Here, we suggest that using the ambipolar property of carbon nanotubes and the threshold modulation ability of dual-gate field-effect transistors, an XOR gate can be constructed in only one transistor. For a traditional XOR gate, 4 to 6 transistors are needed, and this low-footprint topology could be employed in the future for hyperscaling and three-dimensional logic and memory transistor integration.

A Partially Static High Frequency 18T Hybrid Topological Flip-Flop Design for Low Power Application

In this brief, an extremely low power true <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1-\phi $ </tex-math></inline-formula> clocking flip-flop is proposed using eighteen transistors only. The flip-flop is a synchronous bistable element that stores single-bit information. To design this Master Slave (MS) type architecture, topological, logical, and adaptive coupling techniques are employed. The minimum number of transistors are maintained by using above techniques, which comprises of complementary pass transistor logic and static complementary MOS logic. It also offers low power, a low delay that speeds up the flip-flops, and low complexity by reducing the transistor count. The proposed circuit is implemented using Cadence Virtuoso and compared with the five other reported logic structures of flip-flops. The proposed hybrid logic architecture has showed the highest percentage, i.e., 49.73% improvement in terms of power as compared to LRFF. It also improved the delay and energy efficiency (EDP). The Monte Carlo simulation has been performed for C to Q Delay for 20K samples. By reducing the number of PMOS transistors, the total area of the proposed flip-flop reduces by a minimum of 9.49% in comparison to state of the art work. The proposed circuit can work properly within a frequency range upto 1 GHz. It is also compared with reported 18T TSPC flip-flop.

Skyrmions-based logic gates in one single nanotrack completely reconstructed via chirality barrier.

Logic gates based on magnetic elements are promising candidates for logic-in-memory applications with non-volatile data retention, near-zero leakage and scalability. In such spin-based logic devices, however, the multi-strip structure and fewer functions are obstacles to improving integration and reducing energy consumption. Here we propose a skyrmions-based single-nanotrack logic family including AND, OR, NOT, NAND, NOR, XOR and XNOR that can be implemented and reconstructed by building and switching the Dzyaloshinskii-Moriya interaction (DMI) chirality barrier on a racetrack memory. Besides the pinning effect of the DMI chirality barrier on skyrmions, the annihilation, fusion and shunting of two skyrmions with opposite chirality are also achieved and demonstrated via local reversal of the DMI, which are necessary for the design of an engineer programmable logic nanotrack, transistor and complementary racetrack memory.

Yield and leakage current of organic thin-film transistor logic gates toward reliable and low-power operation of large-scale logic circuits for IoT nodes

This paper reports on a strategy for yield improvement and static leakage current reduction by a standard cell design for large-scale organic thin-film transistor (OTFT) circuits. Printable or flexible devices are suitable for IoT nodes, and digital OTFT circuits comprise the peripheral circuits of such devices. Sufficiently high yields and low static power consumptions are essential for battery operations of IoT nodes having functional digital circuits. Our design method to address the weak n-type OTFT on-current results in improved logic gate yields without any cell area increase. We improved the yield of the inverter, NAND, and NOR gates using a standard cell design, and achieved a 100% yield for the inverter and NOR gates and 88% yield for the NAND gates. Signal propagations with the rail-to-rail operation were measured on test chips. Leakage currents of 585 pA and 2.94 nA were achieved for the inverter and NOR gates, respectively.

Low-power and low-energy CNFET-based approximate full adder cell for image processing applications

PurposeFull adder cells are building blocks of arithmetic circuits and affect the performance of the entire digital system. The purpose of this study is to provide a low-power and high-performance full adder cell.Design/methodology/approachApproximate computing is a novel paradigm that is used to design low-power and high-performance circuits. In this paper, a novel 1-bit approximate full adder cell is presented using the combination of complementary metal-oxide-semiconductor, transmission gate and pass transistor logic styles.FindingsSimulation results confirm the superiority of the proposed design in terms of power consumption and power–delay product (PDP) criteria compared to state-of-the-art circuits. Also, the proposed full adder cell is applied in an 8-bit ripple carry adder to accomplish image processing applications including image blending, motion detection and edge detection. The results confirm that the proposed cell has premier compromise and outperforms its counterparts.Originality/valueThe proposed cell consists of only 11 transistors and decreases the switching activity remarkably. Therefore, it is a low-power and low-PDP cell.

2D Materials‐Based Static Random‐Access Memory

2D transition-metal dichalcogenide semiconductors, such as MoS2 and WSe2 , with adequate bandgaps are promising channel materials for ultrascaled logic transistors. This scalability study of 2D material (2DM)-based field-effect transistor (FET) and static random-access memory (SRAM) cells analyzing the impact of layer thickness reveals that the monolayer 2DM FET with superior electrostatics is beneficial for its ability to mitigate the read-write conflict in an SRAM cell at scaled technology nodes (1-2.1nm). Moreover, the monolayer 2DM SRAM exhibits lower cell read access time and write time than the bilayer and trilayer 2DM SRAM cells at fixed leakage power. This simulation predicts that the optimization of 2DM SRAM designed with state-of-the-art contact resistance, mobility, and equivalent oxide thickness leads to excellent stability and operation speed at the 1-nm node. Applying the nanosheet (NS) gate-all-around (GAA) structure to 2DM further reduces cell read access time and write time and improves the area density of the SRAM cells, demonstrating a feasible scaling path beyond Si technology using 2DM NSFETs. In addition to the device design, the process challenges for 2DM NSFETs, including the cost-effective stacking of 2DM layers, formation of electrical contacts, suspended 2DM channels, and GAA structures, are also discussed.

Low power, less occupying area, and improved speed of a 4-bit router/rerouter circuit for low-density parity-check (LDPC) decoders.

Background: Low-density parity-check (LDPC) codes are more error-resistant than other forward error-correcting codes. Existing circuits give high power dissipation, less speed, and more occupying area. This work aimed to propose a better design and performance circuit, even in the presence of noise in the channel. Methods: In this research, the design of the multiplexer and demultiplexer were achieved using pass transistor logic. The target parameters were low power dissipation, improved throughput, and more negligible delay with a minimum area. One of the essential connecting circuits in a decoShder architecture is a multiplexer (MUX) and a demultiplexer (DEMUX) circuit. The design of the MUX and DEMUX contributes significantly to the performance of the decoder. The aim of this paper was the design of a 4 × 1 MUX to route the data bits received from the bit update blocks to the parallel adder circuits and a 1 × 4 DEMUX to receive the input bits from the parallel adder and distribute the output to the bit update blocks in a layered architecture LDPC decoder. The design uses pass transistor logic and achieves the reduction of the number of transistors used. The proposed circuit was designed using the Mentor Graphics CAD tool for 180 nm technology. Results: The parameters of power dissipation, area, and delay were considered crucial parameters for a low power decoder. The circuits were simulated using computer-aided design (CAD) tools, and the results depicted a significantly low power dissipation of 7.06 nW and 5.16 nW for the multiplexer and demultiplexer, respectively. The delay was found to be 100.5 ns (MUX) and 80 ns (DEMUX). Conclusion: This decoder's potential use may be in low-power communication circuits such as handheld devices and Internet of Things (IoT) circuits.

ECONOMIC SIGNIFIANCE AND DESIGN OF LOW AREA AND LOW POWER MAGNITUDE COMPARATOR

Multibit digital comparators take up large surface and high power consumption. As they are composed of logic gates, it is recommended to decrease the number of transistors in the logic gates using different transistor logics. By decreasing the number of transistors, the occupied surface and power consumption of the entire circuit will also decrease. The identical circuit was propounded applying standard CMOS (Complementary MetalOxide-Semiconductor) technology and with a combination of PTL (Pass Transistor Logic) and DVL (Dual Value Logic) transistor logics. Due to less area and decreased number of transistors, the physical design (layout) of the whole circuit will become easier and less time consuming from layout designer point of view, then in case of standard CMOS technology. As an output load was used a 1fF capacitance for both circuits. Correspondingly, the propounded circuit cuts down the power consumption by 21.3%, the delay was decreased by 28.4%, and the number of transistors was reduced by 25%. The circuit was developed using Custom Compiler tool. All the simulations are done using Synopsys Hspice and WaveView tools. SAED (Synopsys Armenia Educational Department) 32/28 nm technology process libraries have been used during the work.

Toward Efficient Logic-in-Memory Computing With Magnetic Reconfigurable Logic Circuits

Logic-in-memory (LIM) structures are promising candidates to obviate limitations of the conventional von Neumann architecture, especially in big data applications, such as image processing. In this paradigm, simple logic operations are embedded in memory to perform basic processes and consequently decrease the workload of the main processor. This letter presents an efficient hybrid fin field-effect transistor and magnetic tunnel junction (MTJ) logic structure compatible with all kinds of memory and which performs <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nor/or</small> and <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nand/and</small> operations. The design utilizes MTJs to obtain different voltage levels and two sense amplifiers to generate the outputs. Simulation results assert that the design improves the delay and power by 33% and 20%, respectively, compared to its state-of-the-art counterparts. Moreover, the magnetic LIM structure is appropriately utilized in image processing applications, such as minimum and maximum image filters, for preparing intermediate data. In the case study, high-level simulations indicate that the design reduces the delay and power by 31% and 21%, respectively.

Arithmetic and Logic Circuits Based on ITO-Stabilized ZnO TFT for Transparent Electronics

In this paper, general logic cell and module designs in basic digital signal processing (DSP), for transparent, flexible chips and wearable electronics are presented. Modified Circuits from ratioed logic and pass transistor logic styles are modified and proposed, based on n-type-only indium tin oxide (ITO) stabilized ZnO thin-film transistors (TFTs) process. Elaborations on logic circuits with purely n-type TFT transistors were carried out to extend the logic swing of circuit outputs and accelerate the signal propagation in complex logic functions with simplified pull-up/pull-down or passive networks. To implement logic complexes on multiple OR-of-ANDs functions with better performance, tailored active controlled ratioed logic style is adopted with faster speed and smaller area by simplifying the transistor networks properly. All the circuits were fabricated on transparent glass plate. The featured 2-input/3-input XOR gate, 4-1 MUX and D flip flop (DFF) can operate with maximum featured delays of 2- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$6~\mu \text{s}$ </tex-math></inline-formula> at 5 V power supply, with comparatively over 50% less delays and areas than other state-of-art works. The featured 4-bit adder performs maximum <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$16.41~\mu \text{s}$ </tex-math></inline-formula> delay at 5 V in measurement. A 4-bit multiplier is also presented based on the adder and DFF. These proposed TFT circuits exhibited smaller area with relatively moderate-high performance in comparison, which were promising building blocks for transparent flexible DSP electronics with low-speed requirements.

THE OUTPUT NOISE REDUCTION OF THE MULTIPLEXER

A new approach to reducing output noises of the multiplexer (MUX) is presented. In contrast to other methods, this one reduces the noise with a strength equal to the strength of the noise in specific cases. The method is based on adding logic cells and transistors in the circuit and choosing its sizes corresponding to the delay time of the output signal and to the strength of the output noise. In general, the main device that is used for reducing output noises in digital and analog circuits it’s capacitor. But in the circuits which scheme structure depends from its bit number, the output noise strength depends from the quantity of the switching inputs of the scheme. As high will be the switching inputs, as bigger will be the strength of the output noises. The same capacitor can keep the accuracy of the output signal in certain cases of switching inputs combinations. Here is developed a method, by which each combination of switching inputs turns on appropriate output elements by which the accuracy of the output signal is saved in any case. The method is very comfortable using in MUX, because its inputs mostly are symmetrical, and it helps to use the method adding the output elements with nearly same sizes. The symmetrical structure of the inputs of the MUX is useful for the method, also observing the input-output signal delay time. By using this method on 2-to-1 MUX designed in 32 nm technology, the area of the circuit increases by 28% and the noise error decreases by 59%.

14-T hybrid full adder design and its implementation for high-performance arithmetic applications

The majority of implemented full adder (FA) circuits are employing separate modules in hybrid logic architecture. The key advantage of employing a hybrid logic architecture for FA cell design is that each module may be individually changed to improve circuit performance. The use of pass transistor logic (PTL) and gate diffusion input (GDI) to create a one-bit hybrid FA cell with outstanding performance is proposed in this study. To ensure optimal performance, the FA circuit is proposed with 14 transistors. Using the virtuoso tool of cadence with gpdk 45 nm process CMOS technology, the circuit is simulated. The proposed 1-bit hybrid FA cell design metrics are compared to the design metrics for the 11 different reported FA circuits. The current study found that, when compared to other FA designs, power delay product (PDP), delay, and power improved by 3–20 %, 15–25 %, and 30–75 %, respectively. Different supply voltages (0.45–1.2 V) are also investigated for the proposed circuit.

Field Programmable Gate Arrays (FPGA) Based Computational Complexity Analysis of Multicarrier Waveforms

Multicarrier waveforms with enhanced spectral efficiency, low latency, and high throughput are required for 5G wireless networks. The Orthogonal Frequency Division Multiplexing (OFDM) method is well-known in research, but due to its limited spectral efficiency, various alternative waveforms are being considered for 5G systems. In the recent communication world, NOMA (non-orthogonal multiple access) plays a significant part due to its wider transmission of data with less bandwidth allocation. Even if a high data rate can be attained, the transmission problem will arise due to the spread of multiple paths. In order to reduce complexity and area utilization, a novel PL-based FWFT (Fast walsh hadamard fourier transform) technique is proposed and implemented in the VLSI architecture. To achieve a high-performance system, the main concept of pass transistor logic (PL) with VLSI implementation is to diminish the size and power consumption. Finally, the performance of the proposed FWFT/ IFWFT implementation has been evaluated. For FPGA’s 16-point FWFT, the number of transistors decreased by 21% and the total power required was reduced by 5.5%. The same implementation for 34 transistor-pass-logic customs and power consumption is 2.764 mW with a latency of 78.256 ns. As a consequence, the proposed system achieves low power, area and low complexity system that can enhance the function of the multicarrier waveform systems.

Improved Monolayer MoS Performance With Two-Step Atomic Layer Deposited High- Dielectrics

Gate dielectric engineering is crucial to enable two-dimensional (2D) transition metal dichalcogenides (TMDs) for logic transistor applications. In this work, we demonstrate a uniform and pinhole-free bilayer high-K fabricated on monolayer (1L) molybdenum disulfide (MoS2) through thermal atomic layer deposition (ALD) without surface pretreatment. A thin low-temperature (75∘C) AlOx film deposited directly on 1L-MoS2 mitigates 2D channel damage and serves as a nucleation and protection layer for high-temperature (250∘aC) HfOx high-K layer. The 1L-MoS2 back-gate (BG) devices with low-temperature ALD capping show minor mobility degradation, less threshold voltage shift, smooth surface topography, and lower device variability compared to those with high-temperature ALD capping. These electrical differences are closely related to the coverage of the AlOx film at the initial ALD stage and the resultant quality of the AlOx -MoS2 interface after HfOx deposition. The underlying mechanism of ALD on the TMDs is proposed in terms of physical analysis and electrical findings. This work provides a practical and scalable ALD approach in gate dielectrics toward high performance 2D electronics.

Digital electronics using dielectric elastomer structures as transistors

Dielectric elastomers (DEs) are soft and stretchable structures that are typically used as actuators, sensors, and energy harvesters and can perform basic signal processing tasks. Thus, they can be used to create multi-functional and autonomous DE structures, with intrinsic information processing capabilities, that require fewer external components. This contribution introduces how to assemble electronic circuits with DEs, in a similar way to how transistors are employed in conventional electronics. The focus is on the design of digital circuits. At first, parallels between digital signal processing with DEs and with conventional transistors are shown. After describing the differences in the working conditions (e.g., working voltages) of the two structures, it is demonstrated that various design techniques, commonly adopted in conventional electronics, can be used to build DE electronics. The functioning is demonstrated by presenting alternative ways of designing NOR and XOR gates, reducing, in the latter case, the number of components required. Moreover, pass transistor logic is employed to realize a DE multiplexer. This work illustrates a consistent method to realize digital circuits with DEs, and it demonstrates how electronic design techniques can be adapted to work with DEs. It shows that DE circuits can be built starting from their conventional counterpart, obtaining improved devices.