ECONOMIC SIGNIFIANCE AND DESIGN OF LOW AREA AND LOW POWER MAGNITUDE COMPARATOR

Abstract

Multibit digital comparators take up large surface and high power consumption. As they are composed of logic gates, it is recommended to decrease the number of transistors in the logic gates using different transistor logics. By decreasing the number of transistors, the occupied surface and power consumption of the entire circuit will also decrease. The identical circuit was propounded applying standard CMOS (Complementary MetalOxide-Semiconductor) technology and with a combination of PTL (Pass Transistor Logic) and DVL (Dual Value Logic) transistor logics. Due to less area and decreased number of transistors, the physical design (layout) of the whole circuit will become easier and less time consuming from layout designer point of view, then in case of standard CMOS technology. As an output load was used a 1fF capacitance for both circuits. Correspondingly, the propounded circuit cuts down the power consumption by 21.3%, the delay was decreased by 28.4%, and the number of transistors was reduced by 25%. The circuit was developed using Custom Compiler tool. All the simulations are done using Synopsys Hspice and WaveView tools. SAED (Synopsys Armenia Educational Department) 32/28 nm technology process libraries have been used during the work.