Transistor Action Research Articles

A multitasking device based on electromagnetically induced transparency in optical cavities

Quantum memories and optical transistors are elementary building blocks for the implementation of many devices for quantum computers and quantum communication. The realization of experiments that can perform both capabilities in the same setup can open an avenue of possibilities in the development of such practical quantum technologies. We theoretically investigate the feasibility of implementing a quantum memory and an optical transistor in the same setup using a combination of electromagnetically induced transparency and cavity quantum electrodynamics (cavity-EIT) for single- and two-sided cavity configurations. This was accomplished by considering a single three-level atom in $$\Lambda $$ configuration coupled to a single electromagnetic mode of the cavity and a suitable temporal shape for the EIT control field. An optical transistor in cavity-EIT can be realized in a symmetric cavity with two output channels while a high efficient quantum memory must be performed in a single-sided one. From the master equation and input–output formalisms for the intracavity and outside fields, respectively, we obtain the upper bound of $$50\%$$ for the memory efficiency with perfect transistor action in two-sided cavities and values close to $$100\%$$ for the efficiency with a limited transistor effect for the single-sided setup in the high cooperativity regime. Thus, we showed that a dual device, which operates as a quantum memory and an optical transistor in the same setup of cavity-EIT, can be accomplished with some limitation in one of those capabilities.

Suppression of the Floating-Body Effect of Vertical-Cell DRAM With the Buried Body Engineering Method

Recently, new dynamic random-access memory (DRAM) structures have been used to sharply reduce chip size. One of these is vertical-cell DRAM that has the advantage of reducing the chip area by 33% compared with the conventional cell DRAM. However, since the bitline is made in Si trenches, it can cause a floating-body effect, which increases the OFF current. Here, we suggest the buried body engineering method as a simple way to deal with these disadvantages without changing the materials. This method significantly improved the electrical performance in comparison with the conventional buried contact. Especially, the OFF current, which is the most important factor influencing the refresh time, was dramatically reduced by a factor of 63. The reason for this dramatic decrease in the OFF current is that the holes accumulated in the body are removed immediately, and they do not generate a parasitic bipolar junction transistor (BJT) action. We also calculated the hole density using simulations and obtained the junction depth that suppresses the floating-body effect. Above all, we provide advanced insight into the mechanism of the parasitic BJT action due to the floating-body effect that occurs at the bottom contact region of vertical-cell DRAM.

Room-temperature electrical control of exciton flux in a van der Waals heterostructure.

Devices that rely on the manipulation of excitons-bound pairs of electrons and holes-hold great promise for realizing efficient interconnects between optical data transmission and electrical processing systems. Although exciton-based transistor actions have been demonstrated successfully in bulk semiconductor-based coupled quantum wells1-3, the low temperature required for their operation limits their practical application. The recent emergence of two-dimensional semiconductors with large exciton binding energies4,5 may lead to excitonic devices and circuits that operate at room temperature. Whereas individual two-dimensional materials have short exciton diffusion lengths, the spatial separation of electrons and holes in different layers in heterostructures could help to overcome this limitation and enable room-temperature operation of mesoscale devices6-8. Here we report excitonic devices made of MoS2-WSe2 van der Waals heterostructures encapsulated in hexagonal boron nitride that demonstrate electrically controlled transistor actions at room temperature. The long-lived nature of the interlayer excitons in our device results in them diffusing over a distance of five micrometres. Within our device, we further demonstrate the ability to manipulate exciton dynamics by creating electrically reconfigurable confining and repulsive potentials for the exciton flux. Our results make a strong case for integrating two-dimensional materials in future excitonic devices to enable operation at room temperature.

Improved Modeling of High Injection Substrate Current in High Voltage Bipolar Transistors

A vertical NPN transistor is typically built on a p-type substrate, which gives rise to parasitic PNP transistor action when the NPN base-collector junction, which is also the PNP emitter-base junction, is forward biased. In Mextram and Hicum, the PNP base terminal is attached to the NPN collector node that corresponds to the epi layer / buried layer interface, with VB1C1 as the PNP control emitter-base voltage, as illustrated in Fig. 1. A long physics based derivation to justify this choice was given in [1]. In Vbic, an option is provided to use both VB1C1 and VBC2 as PNP control voltage, with VBC2 as default. Using B or B1 is insignificant typically, while the difference between C1 and C2 is. While such approach generally works well for high speed transistors, for high voltage transistors, we experience great difficulty in fitting the substrate current at high VBE when the electrical base pushes out towards the collector, causing the internal NPN base-collector junction to be forward biased despite a reverse bias on the NPN external base-collector junction. Holes injected from the base diffuse downward towards the buried layer, and are retarded by a high electric field near the epi/buried layer interface, making the actual physics of hole transport much more complex than in a standalone PNP transistor. Fig. 2 (a) shows the best results one can possibly get with the standard Mextram model for a typical VBE sweep at VBC=0, -2 and -5V, VBS=2V. It is important to note that the VB1C1 = VBC + ICRCC –IBRBC in Mextram terms, with RCC and RBC being extrinsic collector and base resistances, respectively. Fig. 2 (b) shows the simulated VB1C1. For VBC=-2 and -5V, VB1C1 is still largely negative, while in measurement substrate current starts to rise quickly around VBE of 0.8V, indicating a rapid turn on of PNP action. This clearly suggests that the theory of [1] does not apply to these transistors, and improved modeling of PNP is needed. An alternative is to use the intrinsic base-collector junction voltage VB2C2, i.e. VB2C2* in Mextram, as the PNP substrate current control voltage, which was suggested in [2]. This leads to a higher Isub as shown in Fig. 3 (a) and (b). However, the onset of Isub, and the high VBE values of IB are all overestimated. IC is underestimated due to overestimation of IBRBC. This, however, does suggest that the PNP action is in fact related to some kind of internal base-collector junction bias which relates to the epi layer state. Here we propose a new model for the effective PNP emitter-base junction voltage, based on Mextram’s epi layer model. To minimize coupling of PNP and NPN modeling, we create a separate VB2C2, denoted as VB2C2** , and calculate it exactly the same way VB2C2* is calculated from epi layer current IC1C2 and VB2C1, but with a set of dedicated epi layer model parameters, i.e. rcv, scrcv, ihc, axi and vdc. In parameter extraction, the regular epi layer model parameter set is used for fitting Gummel, output and fT curves, while this new set of Isub dedicated epi layer model parameters is used for fitting substrate current. Fig. 4 (a) and (b) show modeling results of our new model. IB and Isub are much better fitted, including accurate modeling of the onset of Isub. [1] W. D. Mack and M. Horowitz, “Measurement of series collector resistance in bipolar transistor,” IEEE J. Solid-State Circuits, vol. SC-17, pp. 767-773, Aug. 1982. [2] J. -S. Park, A. Neugroschel, V. de la Torre and P. J. Zdebel, “Measurement of collector and Emitter Resistances in Bipolar Transistors,” IEEE Transactions on Electron Devices, vol. 38, pp. 365-372, Feb. 1991. Figure 1

Lithium-ion conducting glass ceramics for electrostatic gating

We explore solid electrolytes for electrostatic gating using field-effect transistors (FETs) in which thin WSe2 crystals are exfoliated and transferred onto a lithium-ion conducting glass ceramic substrate. For negative gate voltages (VG < 0), the devices work equally well as ionic liquid gated FETs while offering specific advantages, whereas no transistor action is seen for VG > 0. For VG < 0, the devices can nevertheless be driven into the ambipolar injection regime by applying a large source-drain bias and strong electroluminescence is observed when direct band-gap WSe2 monolayers are used. Detecting and imaging the emitted light is much simpler in these FETs as compared to ionic liquid gated transistors, because the semiconductor surface is exposed (i.e., not covered by another material). Our results show that solid electrolytes are complementary to the existing liquid gates, as they enable experiments that are not possible when the semiconductor is buried under the liquid itself.

All-ion-implanted planar-gate current aperture vertical Ga2O3 MOSFETs with Mg-doped blocking layer

A vertical β-Ga2O3 metal–oxide–semiconductor field-effect transistor featuring a planar-gate architecture is presented. The device was fabricated by an all-ion-implanted process without requiring trench etching or epitaxial regrowth. A Mg-ion-implanted current blocking layer (CBL) provided electrical isolation between the source and the drain except at an aperture opening through which drain current was conducted. Successful transistor action was realized by gating a Si-ion-implanted channel above the CBL. Thermal diffusion of Mg induced a large source–drain leakage current through the CBL, which resulted in compromised off-state device characteristics as well as a reduced peak extrinsic transconductance compared with the results of simulations.

Efficient All-Optical Transistor Action in Short-Length Multimode Optical Fibers

The quest for realizing an all-optical transistor while fulfilling desired criteria has been around since long time. Various schemes have been put forward over the years to achieve it; however, almost all techniques make use of at least two different laser sources. Optical event horizon principle has also been employed to see transistor action in glass fibers using two different frequency sources. In this paper, we report an optical transistor action in short-length, tailor-made multimode optical fibers through a single pump only. The higher order mode properties of the fiber and intermodal nonlinear interaction (mainly cross-phase modulation) are used to achieve efficient transistor action. Both the soliton and a weak dispersive pulse are excited in $ LP_{02}$ and $ LP_{01}$ modes of the fiber, respectively, with a certain temporal delay set by the sign of the differential group delay between the modes. We believe that the scheme has potential to improve system performance owing to the fact that only a single-wavelength pump source is required as opposed to the optical-transistor devices available till date that essentially require two-color pumping.

Discharge Characteristics of a Triple-Well Diode-String ESD Clamp

In this work, DC and transient characteristics of a 4 diode string utilizing triple-well technologies as a VDD-VSS clamp device for ESD protection are analyzed in detail based on 2-dimensional device and mixed-mode simulations. It is shown that there exists parasitic pnp bipolar transistor action in this device leading to a sudden increase in DC substrate leakage if anode bias is getting high. Through transient simulations for a 2000 V PS-mode HBM ESD discharge event, it is shown that the dominant discharge path is the one formed by a parasitic pnpn thyristor and a parasitic npn bipolar transistor in series. Percentage ratios of the various current components regarding the anode current at its current peaking are provided. The mechanisms involved in ESD discharge inside the diode-string clamp utilizing triple-well technologies are explained in detail, which has never been done anywhere in the literature based on simulations or measurements.

A Tunnel Dielectric-Based Junctionless Transistor With Reduced Parasitic BJT Action

In this paper, we demonstrate a tunnel dielectric-based junctionless transistor, referred as TD JLT, which consists of a thin dielectric layer in the middle of the channel region of a JLT leading to a drastically reduced parasitic bipolar junction transistor (BJT) action. Using calibrated 2-D simulations, we show that the proposed TD JLT has a significantly low off-state leakage current due to the presence of a tunneling barrier, and an enhanced source-to-channel barrier height, which results in a diminished parasitic BJT action in the off-state. Further, the proposed TD JLT exhibits an extremely high $I_{{{ \mathrm{\scriptscriptstyle ON}}}}/I_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of $\sim 1.1 \times 10^{{{\sf{ 7}}}}$ for a channel length of 20 nm and a significant( $I_{ \mathrm{\scriptscriptstyle ON}}/I_{ \mathrm{\scriptscriptstyle OFF}})$ ratio of $\sim 10^{{{\sf{ 2}}}}$ even for a channel length of 10 nm.

Intermodal nonlinear effects mediated optical event horizon in short-length multimode fiber

The group-velocity-led optical event horizon (OEH) in optical fibers provides a convenient way to efficiently control a weak dispersive pulse by a comparatively strong solitonic pulse. State-of-the-art experiments demonstrating OEH make use of two different light sources, which increases the system complexity and cost. Here, we propose an elegant and cost-effective approach to observe the OEH through intermodal nonlinear interaction between azimuthally symmetric ${\text{LP}}_{01}$ and ${\text{LP}}_{02}$ modes of a specially designed triple-clad multimode fiber through only a single pump. The simultaneous control over dispersion and the walk off of ${\text{LP}}_{01}$ and ${\text{LP}}_{02}$ modes of the designed fiber pave the way for the OEH interaction. The ${\text{LP}}_{02}$ mode possesses anomalous dispersion, while the ${\text{LP}}_{01}$ mode exhibits normal dispersion over the wavelength range of interest. Depending upon the location of the input pump wavelength, the ${\text{LP}}_{02}$ soliton can reflect a weak copropagating ${\text{LP}}_{01}$ dispersive pulse, which possesses the same carrier wavelength as the soliton. The findings of this work might be useful for all-optical switching and also for the optical transistor action, where the increased feasibility is obtained by the fact that the proposed approach does not require separate input wavelengths for the soliton and the dispersive pulse. Moreover, a tunable pump source can be used to observe either a redshift or a blueshift in the dispersive pulse.

Logic Circuits With Hydrogenated Diamond Field-Effect Transistors

As a first step to develop a diamond integrated circuit, hydrogenated diamond not and nor logic circuits composed of depletion-mode (D-mode) and enhancement-mode (E-mode) metal–oxide–semiconductor field-effect transistors (MOSFETs) are fabricated. The D- and E-modes MOSFETs act as load and driver devices for the logic circuits, respectively, which provides complementary transistor actions. The extrinsic transconductance maxima for both the MOSFETs are almost the same value of 17 mS mm $^{-1}$ and insensitive to device processing. With supply voltage changing from −5 to −25 V, gain maximum for not logic circuit increases from 1.2 to 26.1. The nor logic circuit shows clear nor gate characteristics.

Nanotube Junctionless FET: Proposal, Design, and Investigation

In this paper, we propose a nanotube (NT) JLFET for significantly improved performance in the sub-10-nm regime. We show that the tunneling width at the channel-drain interface and the source-to-channel barrier height are considerably increased in the NT JLFET due to the presence of the core gate. Therefore, the lateral band-to-band-tunneling-induced parasitic bipolar junction transistor action is diminished in the off-state of NT JLFET, leading to a significantly high on-state to off-state current ratio of ~107 even for a channel length of 7 nm. Furthermore, we demonstrate that the spacer length and dielectric constant and the core gate diameter can be used as design parameters to further improve the performance of the NT JLFETs. Therefore, we also provide the necessary design guidelines for NT JLFETs.

Diameter Dependence of Leakage Current in Nanowire Junctionless Field Effect Transistors

In this paper, we give a physical insight into the diameter-dependent dominant leakage mechanisms in the nanowire junctionless (NWJL) FETs. Using calibrated 3-D simulations, we show that the off-state current in the NWJLFETs with nanowire diameter less than 10 nm is governed by the drain-induced barrier lowering and the consequent source-to-channel barrier height and barrier thinning, which controls the lateral band-to-band tunneling (L-BTBT)-induced parasitic bipolar junction transistor (BJT) action. Furthermore, the quantum confinement-induced bandgap enhancement is shown to lower the probability of L-BTBT, and hence acts as the dominant mechanism in reducing the off-state current of the NWJLFETs with sub-7 nm diameter. In addition, the hole accumulation due to L-BTBT induces a shielding effect, which results in an inefficient volume depletion, leading to a large off-state current in NWJLFETs with nanowire diameters >15 nm. Furthermore, the impact of gate sidewall spacer on the L-BTBT-induced parasitic BJT in NWJLFETs has also been investigated.

Symmetric Operation in an Extended Back Gate JLFET for Scaling to the 5-nm Regime Considering Quantum Confinement Effects

In this paper, we propose a double gate junctionless FET (DGJLFET) with an extended back gate (EBG) architecture for significantly improved performance in the sub-10-nm regime. Even for a channel length of 5 nm, we show using calibrated 2-D simulations that the EBG DGJLFET, when compared with the DGJLFET, exhibits: 1) an improved subthreshold swing; 2) a significantly low off-state leakage current; and 3) a considerably high $I_{\mathrm{\scriptscriptstyle ON}}/I_{{\mathrm{\scriptscriptstyle OFF}}}$ ratio of $\sim 10^{8}$ . Furthermore, we demonstrate, for the first time, that the quantum confinement-induced bandgap widening diminishes the parasitic bipolar junction transistor (BJT) action and, therefore, facilitates the scaling of the conventional DGJLFETs to the sub-5-nm channel regime where the quantization effects are significant. Moreover, we also show, for the first time, that the DG junctionless accumulation mode FET suffers from an enhanced parasitic BJT action and, therefore, a significantly high off-state leakage current compared with the DGJLFET. In addition, we demonstrate that the loss of gate control for negative gate voltages in the DGJLFETs with larger silicon film doping ( $N_{D} \geq 2 \times 10^{19}$ cm $^{-3}$ ) is due to a shielding effect initiated by the band-to-band tunneling.

Junctionless nanowire TFET with built-in N-P-N bipolar action: Physics and operational principle

In this paper, we present a novel junctionless nanowire tunneling FET (JN-TFET) in which the source region is divided into an n+ as well as a p+ type region. We will show that this structure can provide a built-in n-p-n bipolar junction transistor (BJT) action in the on state of the device. In this regime, tunneling of electrons from the source valence band into the channel conduction band enhances the hole concentration in the p+ source region. Also, the potential in this region is increased, which drives a built-in BJT transistor by forward biasing the base-emitter junction. Thus, the BJT current adds up to the normal tunneling current in the JN-TFET. Owing to the sharp switching of the JN-TFET and the high BJT current gain, the overall performance of the device, herein called “BJN-TFET,” is improved. On-state currents as high as 2.17 × 10−6 A/μm and subthreshold swings as low as ∼50 mV/dec at VDS = 1 V are achieved.

Memory and negative-resistance effects in a strained metal-gate high-k n-type field-effect-transistor from 375 K down to 77 K

We introduce an experimental alternative way of looking into the charging and discharging mechanism inside a high-k stacked oxide of a metal-gate strained n-type Field-Effect-Transistor (nFET). This alternative way reproduces a memory and negative resistance effect by biasing the nFET device in a non-conventional way. This is achieved by forward-biasing the drain-bulk junction and by setting the gate electrode in a high-impedance mode. The produced negative resistance effect (NRE) has a controllable peak-to-valley current ratio (PVCR) that goes from about 3.0 up to a value of 5.5 at room temperature. The PVCR increases up to 8.35 at T = 225 K and reduces to 2.84 at T = 375 K in a linear trend. The memory effect is observed when the drain-bulk junction voltage is swept from low to high values and back from high to low values. From low to high forward drain-bulk bias the NRE shows up and vanishes when coming back from high to low forward drain-bulk bias. The NRE and memory effects are attributed to a coupled-gate oxide charging/discharging mechanism with an induced bipolar transistor action in the channel of the FET.

Raised Source/Drain Dopingless Junctionless Accumulation Mode FET: Design and Analysis

We design and analyze a raised source/drain dopingless junctionless accumulation mode FET (RDJAMFET) on an intrinsic silicon film using charge plasma concept. This device does not have any physical doping or junctions. Using 2-D simulations, we demonstrate that by making use of the physical design parameters, the device can achieve reduced band-to-band tunneling-induced parasitic bipolar transistor action in the off-state as compared with the planar dopingless junctionless FET (DJFET) for sub-20-nm channel length devices. Further, the RDJAMFET has better gate control and shows significant improvements in terms of drain-induced barrier lowering, subthreshold swing, and $I_{\mathrm{\scriptscriptstyle ON}}$ / $I_{\mathrm{\scriptscriptstyle OFF}}$ as compared with the DJFET for sub-20-nm channel length devices.

Controlling L-BTBT and Volume Depletion in Nanowire JLFETs Using Core–Shell Architecture

In this paper, we propose the use of a p+ core in the core–shell nanowire (CS NW) architecture to significantly reduce the gate induced drain leakage and therefore, increase the ON-state to OFF-state current ratio ( $I_{{\mathrm{\scriptscriptstyle ON}}}/I_{{\mathrm{\scriptscriptstyle OFF}}}$ ) in n-NW junctionless FETs (NWJLFETs). We show that the lateral band-to-band tunneling induced parasitic bipolar junction transistor action is diminished in the CSJLFET due to an enhanced tunneling width and a higher source to channel barrier height. Further, we also demonstrate that the p+ core helps to realize efficient volume depletion in NWJLFETs with large NW width. Using calibrated 3-D simulations, we show that the CSJLFET exhibits a significantly high ON-state to OFF-state current ratio ( $I_{{\mathrm{\scriptscriptstyle ON}}}/I_{{\mathrm{\scriptscriptstyle OFF}}}$ ) of $\sim 10^{7}$ even for a channel length of 7 nm.

(Invited) Transistors, Integrated Circuits and Nano-Technology: A Historical Review

Bardeen and Brattain, following a suggestion by Gibney on Nov. 17th, 1947, successfully negated the influence of surface states on Nov 21st and, on Dec 16th, achieved transistor action – point-contact semiconductor amplification (of minority-carriers) in polycrystalline Ge. Bardeen and Brattain’s Magic Month was followed by Shockley’s Magic Month, which culminated with Shockley’s minority-carrier injection (Jan 23rd 1948) over the electrostatic barrier at the source / base interface, into the base where the minority-carriers were transported across the base en route to being accumulated at the collector in the polycrystalline Ge sample. Indeed, although all the principals involved were looking to develop a majority-carrier device, their minds were amply prepared to absorb the lessons they learned with the minority-carriers and the resulting new solid-state electronics era was initiated.

Wafer-scale monodomain films of spontaneously aligned single-walled carbon nanotubes.

The one-dimensional character of electrons, phonons and excitons in individual single-walled carbon nanotubes leads to extremely anisotropic electronic, thermal and optical properties. However, despite significant efforts to develop ways to produce large-scale architectures of aligned nanotubes, macroscopic manifestations of such properties remain limited. Here, we show that large (>cm(2)) monodomain films of aligned single-walled carbon nanotubes can be prepared using slow vacuum filtration. The produced films are globally aligned within ±1.5° (a nematic order parameter of ∼1) and are highly packed, containing 1 × 10(6) nanotubes in a cross-sectional area of 1 μm(2). The method works for nanotubes synthesized by various methods, and film thickness is controllable from a few nanometres to ∼100 nm. We use the approach to create ideal polarizers in the terahertz frequency range and, by combining the method with recently developed sorting techniques, highly aligned and chirality-enriched nanotube thin-film devices. Semiconductor-enriched devices exhibit polarized light emission and polarization-dependent photocurrent, as well as anisotropic conductivities and transistor action with high on/off ratios.