Transient Faults Research Articles

A Minimizing Energy Consumption Scheme for Real-Time Embedded System Based on Metaheuristic Optimization

With the widespread application of real-time embedded systems, the contradiction between the energy consumption requirements of modern processors and the limited battery capacity becomes more obvious. Dynamic voltage scaling (DVS) has been proven to be one of the most effective technologies for energy management. However, recent studies have shown that the use of DVS leads to a significant increase in the transient fault rate of processors as the characteristic size of logic gates (or transistors) gets smaller and smaller. In this paper, we consider the problem of assigning processing frequencies to a group of periodic real-time tasks so as to minimize the overall energy consumption under the constraints of time and reliability. Firstly, under the DVS, we take the reliability of the embedded systems into consideration through the regularization terms and present the energy consumption optimization model based on the meta-heuristic algorithms. Secondly, a novel algorithm for adaptive differential whale swarm optimization (ADWOA) is proposed according to the optimization requirements. Finally, the optimized data are saved on the chain through the storable feature of the blockchain for the necessary queries. It is worth noting that the on-chain data contains the intrinsic characteristics of the embedded system, which may give rise to the disclosure of processor privacy. Therefore, we come up with the differential privacy on-chain creating algorithm (DPCA) to protect the privacy of data on the chain. Experimental results show that ADWOA can minimize the energy consumption in real-time embedded system on the premise of ensuring system reliability and privacy.

Identification model for weak areas of transient energy balance in EESs based on dynamic grid partitioning

In response to the high uncertainty of large-scale new energy output in the electrical energy system (EES) and the weak controllability of energy output at multiple time scales, this paper proposes a weak grid identification model for transient energy balance in EESs based on grid partitioning, which has an increasingly complex impact on the weak areas of transient energy balance in the sending-end network. First, the accumulation of port energy during transient faults and the propagation mechanism of port energy in the sending-end system were studied, and an EES transient energy propagation mechanism model was established. Then, considering the energy balance support requirements of nodes, an EES grid partitioning model was established. Afterward, based on the characteristics of transient energy propagation and a grid partitioning model, an identification model for weak areas of transient energy balance in EESs was constructed. Finally, based on actual operating data, numerical simulations were conducted, and the results showed that the proposed weak grid identification model for transient energy balance can meet the requirements for transient stability analysis and transient energy balance characteristic analysis during actual operation of power grids.

Intelligent Fault Diagnosis of Liquid Rocket Engine via Interpretable LSTM with Multisensory Data

Fault diagnosis is essential for high energy systems such as liquid rocket engines (LREs) due to harsh thermal and mechanical working environment. In this study, a novel method based on one-dimension Convolutional Neural Network (1D-CNN) and interpretable bidirectional Long Short-term Memory (LSTM) is proposed for intelligent fault diagnosis of LREs. 1D-CNN is responsible for extracting sequential signals collected from multi sensors. Then the interpretable LSTM is developed to model the extracted features, which contributes to modeling the temporal information. The proposed method was executed for fault diagnosis using the simulated measurement data of the LRE mathematical model. The results demonstrate the proposed algorithm outperforms other methods in terms of accuracy of fault diagnosis. Through experimental verification, the method proposed in this paper was compared with CNN, 1DCNN-SVM and CNN-LSTM in terms of LRE startup transient fault recognition performance. The model proposed in this paper had the highest fault recognition accuracy (97.39%).

A high-speed quadruple-node-upset-tolerant latch in 22 nm CMOS technology

With the scaling of CMOS feature size, the multi-node upset caused by radiation has become an important reliability issue of storage devices. In order to improve the robustness of the storage devices, this paper proposes a High-Speed Quadruple-Node-Upset tolerant latch (HS-QNU). The proposed HS-QNU latch consists of two single-node-upset-resilient RFCs, two single-node-upset-resilient DICEs and a clocked quadruple-input C-element. Based on the single-node-upset-resilient ability of DICE and RFC and the blocking ability of C-element, the proposed HS-QNU latch can effectively tolerate soft errors when any four internal nodes upset by transient faults at the same time. Meanwhile, the latch effectively reduces delay and power consumption by using high-speed path and clock-gating technique. Extensive SPICE simulation in 22 nm CMOS technology shows that compared with QNUTL, the proposed latch reduces delay by 30.68 %, reduces power consumption by 30.86 %, reduces power-delay-product by 52.07 %, reduces area-power-delay-product by 49.08 %, and only increases area overhead by 6.25 %. The proposed HS-QNU latch achieves good tradeoff among delay, power consumption and area. Compared with the previous hardened latches, the proposed HS-QNU latch has the best hardening ability, the highest speed and the smallest power-delay-product. The variation analysis shows that the proposed HS-QNU latch is insensitive to temperature and voltage variations.

Error‐correcting cryptographic S‐boxes with multiple error detection and correction

SummaryIn this paper, the error‐correcting 4‐bit S‐boxes for cryptography applications with multiple error detection and correction are presented. Three 4‐bit S‐boxes which are used in the lightweight block ciphers PRESENT, Midori, and KLEIN are considered for implementation of the error‐correcting method. The proposed method does not require two redundant S‐boxes for repairing the S‐box. The main circuit of the S‐box is implemented concurrently with the low‐cost error‐correcting part of the structure. This reduces the overall area consumption and delay of the proposed error‐correcting method (the area consists of the 4‐bit S‐box and self‐checking/error‐correcting circuits). In the proposed error‐correcting method, the outputs of the S‐box are tested individually and it can detect and repair transient and permanent faults simultaneously. Therefore, the structure can detect and repair the single, double, triple, and quadruple faults at a time. The area and timing results, in 180 nm CMOS technology, show the proposed structures are acceptable in terms of area and delay overheads than those of the other methods.

Adaptive single-phase auto-reclosing scheme based on the moving average filter-quadrature signal generator for transmission lines with shunt reactors

An adaptive single-phase auto-reclosing method based on the moving average filter (MAF)-quadrature signal generator (QSG) is developed to determine secondary arc extinction time for high-voltage transmission lines with shunt reactors. Firstly, the difference between permanent and transient faults is derived and analyzed by the equivalent circuit model. Then, MAF-QSG is utilized to extract these features from the fault voltage. During the second arc period, for transient fault, the fundamental component and subharmonic component with around 50 Hz are reserved by MAF-QSG; however, in the case of permanent fault, only the fundamental component is retained. Finally, the identification index and its threshold are designed above the extraction fault features. The performance of the proposed method is evaluated by simulation and field data studies, accounting for different transmission line compensation levels, transition resistances, and fault location conditions.

Self-Repairing Corrective Control for Input/Output Asynchronous Sequential Machines With Transient Faults

Fault-tolerant corrective control for input/output asynchronous sequential machines (ASMs) is studied in this article. In the present problem setting, not only the controlled ASM but also the corrective controller itself is vulnerable to transient faults. The fault outcome is aggravated when the transient fault occurs to the controller, since the adverse effect of the fault is propagated toward the controlled ASM. We first address a scheme of diagnosing transient faults by designing the state observer that induces the resultant faulty state based on the output burst. We then present the existence condition and design algorithm for a corrective controller that recovers the normal behavior of the closed-loop system against transient faults at the ASM, while achieving self-repair against those faults occurring to the controller. Hardware experiments on field-programmable gate array (FPGA) circuits are provided to validate the applicability of the proposed control methodology.

DESCO: Decomposition-Based Co-Design to Improve Fault Tolerance of Security-Critical Tasks in Cyber Physical Systems

Confidentiality-Specific Faults (CSFs) will put cyber physical systems in threat, since they can result in corrupted information or even retrieve the cryptographic key of security-critical applications. In this paper, we will look into fault-tolerant co-design optimization for security-critical cyber physical systems with resource constraints, such that the encryption/decryption of confidential messages are protected against transient CSF faults. We consider imperfect fault detection mechanisms to identify transient CSF faults happened on confidentiality protection, and utilize duplication code to recovery from such faults. We utilize FPGA to accelerate the executions of security tasks, reducing the overheads of fault-tolerant implementations. The system-level design problem is formulated as a two-objective optimization problem, i.e., to minimize the average reliability degradation of the fault tolerant assignments and to minimize the balanced degree of the reliability degradation, subject to available FPGA budget, deadline, and application execution constraints. Since finding Pareto-optimal solutions is NP-hard, we propose an improved multi-objective optimization algorithm, called DEcomposition-based Security Co-design Optimization (DESCO), to search for Pareto-optimal solutions of fault-tolerant assignments. Experimental results demonstrate that DESCO is effective and can outperform other candidates, proving that our approach is promising in dealing with system-level optimization problem for security-critical applications on cyber physical systems.

Analisis Pelepasan Beban Sistem Jaringan Bengkulu dengan Penambahan PLTU Teluk Sepang 2x100 MW

Load shedding is one way to overcome the rapid decrease in frequency due to transient disturbances. With load shedding the rate of decrease in system frequency can be slowed down so as to avoid total blackouts in the power system. Currently, the Bengkulu network system has added a new power plant, namely PLTU 2 x 100 MW in Teluk Sepang. This paper analyzes load shedding on the Bengkulu network system after the inclusion of PLTU Teluk Sepang. The proposed method is load shedding taking into account the Rate Of Change Of Frequency (ROCOF) and critical fault clearing time (CCT) after a transient fault occurs and then analyzing the stability of the system transient before and after the load shedding occurs with three phase short circuit disturbance. The analysis found that the proposed method succeeded in returning the dropped frequency to the permitted frequency value and the system showed a stable response after a transient disturbance occurred.

High-Speed Hardware Architecture Based on Error Detection for KECCAK.

The hash function KECCAK integrity algorithm is implemented in cryptographic systems to provide high security for any circuit requiring integrity and protect the transmitted data. Fault attacks, which can extricate confidential data, are one of the most effective physical attacks against KECCAK hardware. Several KECCAK fault detection systems have been proposed to counteract fault attacks. The present research proposes a modified KECCAK architecture and scrambling algorithm to protect against fault injection attacks. Thus, the KECCAK round is modified so that it consists of two parts with input and pipeline registers. The scheme is independent of the KECCAK design. Iterative and pipeline designs are both protected by it. To test the resilience of the suggested detection system approach fault attacks, we conduct permanent as well as transient fault attacks, and we evaluate the fault detection capabilities (99.9999% for transient faults and 99.999905% for permanent faults). The KECCAK fault detection scheme is modeled using VHDL language and implemented on an FPGA hardware board. The experimental results show that our technique effectively secures the KECCAK design. It can be carried out with little difficulty. In addition, the experimental FPGA results demonstrate the proposed KECCAK detection scheme's low area burden, high efficiency and working frequency.

A fault-tolerant resource locking protocol for multiprocessor real-time systems

This paper presents the first fault-tolerant resource locking protocol for multiprocessor real-time systems. Resource locking protocols control access to shared resources in real-time systems. Most of the previous studies in resource locking protocols have focused on decreasing blocking time and resource conflicts. The use of such protocols in multiprocessor safety-critical real-time systems necessitates fault tolerance in the design of these systems. However, in research focused on multiprocessor real-time systems, fault tolerance has received low attention in resource allocation studies. In addition, many solutions proposed to improve the reliability in real-time scheduling ignored resource models in their task model. This paper proposes a novel fault-tolerant resource locking protocol, called FTPIA-NPCS, which considers transient faults in shared resources. FTPIA-NPCS proposes a checkpointing-based fault-tolerant mechanism to recover from errors caused by transient faults. In this mechanism, a checkpoint is taken from the tasks, before each resource allocation. In addition to providing fault tolerance, FTPIA-NPCS solves the problem of priority inversion in NPCS protocol for periodic tasks with hard deadlines. The simulation results demonstrate that FTPIA-NPCS tolerates at least one transient fault in resources for each execution of the periodic tasks with 15% blocking time overhead in comparison to its non-fault-tolerant configuration, called PIA-NPCS. Furthermore, the blocking time of higher-priority tasks is minimized in comparison to PIA-NPCS. An analytical evaluation of the protocol supports the simulation results.

Enhancing River Monitoring Embedded System using Time Redundancy Fault Tolerance to Resolve Transient Sensor Fault

Reading data from sensors in the context of the Internet of Things (IoT) is one of the main parameters of a high-reliability system. Data reading by sensors is prone to errors due to various variables that the problem cannot accommodate. One method to overcome this problem is the time redundancy algorithm, where the sensor takes data and its best value several times. In this study, the sensors used to calculate the water levels are ultrasonic sensors and resistance. At the river monitoring point, data is sent using the UDP (User Datagram Protocol) protocol that previous studies have used. This research has been done as a prototype with a maximum distance between sensor nodes of one meter. The results of sending data using UDP were successful, with an average delay of 3293 microseconds. And the ultrasonic sensor that has been tested based on transient fault against time redundancy has an accuracy of 94.5% based on a sampling delay of 1000ms.

A Faulty Line Selection Method for Flexible Grounding System Based on Transient Fault Data

In view of the problem of high-impedance grounding faults (HIFs) in flexible grounding systems (FGS), a faulty line selection method based on transient waveform slope is proposed in this paper. The change of zero sequence (ZS) current of faulty line and non-faulty line (before and after the neutral point parallel small resistance are put in) are analyzed. After the parallel small resistance is put into operation, the waveform slope curve of the transient zero sequence current of each line is obtained, and the modified Hausdorff distance (MHD) algorithm is used to obtain the transient slope matrix. The faulty line is identified by comparing the sizes of each row of elements in the matrix. Simulation verifies the effectiveness of the proposed faulty line selection method.

Anatomy of On-Chip Memory Hardware Fault Effects Across the Layers

Reliability evaluation of a microprocessor design may reveal vulnerable silicon areas that require protection against faults, but also hardware structures that are inherently more resilient to faults. In this work, we revisit the concept of system vulnerability stack by analyzing the anatomy of fault effects across the abstraction layers and identify the sources of error in well-established transient fault vulnerability evaluation methodologies. By providing insights for all distinct system layers, we showcase that the evaluation should take into consideration all faults that arrive from the underlying hardware as well as their distribution. We additionally quantify the level of error in a PVF estimation that can be attributed to the microarchitecture and the architecture. Current established methodologies fail to capture these aspects and can potentially lead to misleading findings. We experimentally show how PVF estimation can follow opposite (and thus misleading) trends compared to the correct, full-stack Architectural Vulnerability Factor (AVF) estimation and explain the reasons why the higher-level methodologies provide diverging results by showing the anatomy of faults manifestation across the layers. Our experiments are performed on an Armv8 microprocessor model, using different input datasets to thoroughly demonstrate our insights.

Atmospheric Neutron-Induced Fault Generation and Propagation in Quantum Bits and Quantum Circuits

Quantum Computing, by exploiting the quantum properties of quantum bits, significantly improves the performance and efficiency of computation. Unfortunately, quantum devices are very susceptible to external perturbation, including natural radiation. In this paper we measure, through GEANT4 simulations, the charge deposited by impinging neutrons in superconducting quantum devices. As we show, most atmospheric neutrons deposit sufficient energy to break Cooper pairs and, thus, can potentially modify the qubit state. Then, with a dedicated circuit-level fault-injector, we track the transient fault propagation in real quantum circuits and measure its impact on the output probabilities distribution. We discuss the fault model for quantum bits and show how to measure faults impact on the circuit output.

Analysis of the Causes of Outages in the Distribution System of Lagos State, Nigeria

The distribution system is essential in the provision of electricity for all consumers. However, outages occasioned by faults are a major setback in ensuring a regular supply of electricity to consumers in a populous state like Lagos. This study analyses the outage causes, their cost, energy loss, and duration of outages experienced by electricity consumers in the distribution systems of Lagos State. The fault reports of Eko Electricity Distribution Company (EKEDC) and Ikeja Electricity Distribution Company (IKEDC) were used for the analysis. The analysis revealed that the main causes of outages on the network are transient faults (356.78 occurrences per month) and jumper cuts (352.83 occurrences per month). The average monthly cost impacts of the outages on the network are estimated to be between ₦631m & ₦837m and ₦837m & ₦1.66b for the 11kV and 33kV networks of the State respectively. The average monthly energy lost due to outages on the network for the period under review is significant (100,415.34 MWh in total) while the average monthly duration of the outages is notably high (28,463.34 hours in total). To minimise outages and their impacts, faults should be cleared on time while the lines are patrolled and maintained regularly. The jumpers should be replaced with metal line taps or bi-metal line taps while intermediate poles are introduced in over-spanned lines to minimise transient fault on the network of the State.

Utilization and criticality based fault-tolerant scheduling in multicore mixed critical systems

PurposeThe main purpose of the paper is timing analysis of mixed critical applications on the multicore system to identify an efficient task scheduling mechanism to achieve three main objectives improving schedulability, achieving reliability and minimizing the number of cores used. The rise in transient faults in embedded systems due to the use of low-cost processors has led to the use of fault-tolerant scheduling and mapping techniques.Design/methodology/approachThe paper opted for a simulation-based study. The simulation of mixed critical applications, like air traffic control systems and synthetic workloads, is carried out using a litmus-real time testbed on an Ubuntu machine. The heuristic algorithms for task allocation based on utilization factors and task criticalities are proposed for partitioned approaches with multiple objectives.FindingsBoth partitioned earliest deadline first (EDF) with the utilization-based heuristic and EDF-virtual deadline (VD) with a criticality-based heuristic for allocation works well, as it schedules the air traffic system with a 98% success ratio (SR) using only three processor cores with transient faults being handled by the active backup of the tasks. With synthetic task loads, the proposed criticality-based heuristic works well with EDF-VD, as the SR is 94%. The validation of the proposed heuristic is done with a global and partitioned approach of scheduling, considering active backups to make the system reliable. There is an improvement in SR by 11% as compared to the global approach and a 17% improvement in comparison with the partitioned fixed-priority approach with only three processor cores being used.Research limitations/implicationsThe simulations of mixed critical tasks are carried out on a real-time kernel based on Linux and are generalizable in Linux-based environments.Practical implicationsThe rise in transient faults in embedded systems due to the use of low-cost processors has led to the use of fault-tolerant scheduling and mapping techniques.Originality/valueThis paper fulfills an identified need to have multi-objective task scheduling in a mixed critical system. The timing analysis helps to identify performance risks and assess alternative architectures used to achieve reliability in terms of transient faults.

Faulty Feeder Identification Method Considering Inverter Transformer Effects in Converter Dominated Distribution Network

With the increase in inverter interfaced distribution generations (IIDGs), converter-dominated distribution networks (CDDNs) are expected. When a single-phase-to-earth (SPE) fault occurs in a CDDN, since the inverter transformer effects can affect the transient fault characteristics of fault signals, the existing faulty feeder detection techniques may not be applicable. This paper focuses on the inverter transformer effects on transient zero sequence currents (TZSCs). First, the inverter transformer effects on TZSCs are analyzed, and the analytical expressions of TZSCs are derived. It is found that the transient fault characteristics in TZSCs may become weak by considering the inverter transformer effects. As a result, the accuracy and reliability of faulty feeder detection face more challenges. To address this issue, a novel faulty feeder identification method based on the first order accumulated generating operator (AGO) method and improved cosine similarity is proposed. The effectiveness and applicability of the proposed method are validated in the converter-dominated distribution network. Additionally, the field test results also indicate the feasibility of the proposed method.

A new reclose function for distribution network based on phase-controlled technology

When a short-circuit fault occurs in a power system, the peak value of the fault current is typically high, causing negative effects, such as insulation aging. The auto-reclose function is effective in reducing the impact of transient faults and has been widely used to improve power supply reliability. In the traditional reclose function, the fault current exists several cycles after reclosing. This is because of the fault diagnosis process, response time of the protective device, and arc duration. To resolve this problem, a new reclose function for distribution networks is proposed in this paper. In the proposed reclose function, a fast making–breaking operation is performed to obtain the test current before closing. The hold-on time of the circuit breaker (CB) is controlled in one cycle using phase-controlled technology. Because of the short duration of test current, a fault diagnosis method considering both the value and distortion degree of test current is proposed to improve the effectiveness of fault diagnosis. The characteristics of test current are obtained theoretically based on an equivalent resistance-inductor-capacitor series circuit. The “making” command is only sent to CBs when a transient fault occurs. The simulation and experimental results show that the proposed function can significantly reduce the influence of the fault current when a permanent short-circuit fault occurs in the power system.

Self-Isolation of Faulted Section from Closed loop Distribution System Using HHO for WSN-Based Smart Grids

Raining, fog, lightning, insulation failure and short circuit are the major reason for fault occurrence in smart grids of distribution systems. This work arranges the distribution system as a radial network (closed loop structure). Generally, the radial network is suffered from both transient and permanent faults. This work uses the harris hawks optimization (HHO) algorithm to find and isolate such faults. Self-isolation separates faulted sections from the distribution system to provide a nonstop power supply. Accurate self-identification and permanent isolation of faulty sections are the main objective functions of HHO, which reduces the complexity and energy loss of the self-isolation process. The harris hawks optimized self-isolation (HHOSI) algorithm continuously monitors the smart grid relays, switches and circuit breakers through a wireless sensor network (WSN) to identify the faulty part. The proposed algorithm is implemented in the MATLAB platform and analyzed the performance of a self-isolation scheme for 5 minutes. As a result, the proposed method attains 32.38% performance improvement over AEC and 18.06% over the LO-ADI method.