Anatomy of On-Chip Memory Hardware Fault Effects Across the Layers

Abstract

Reliability evaluation of a microprocessor design may reveal vulnerable silicon areas that require protection against faults, but also hardware structures that are inherently more resilient to faults. In this work, we revisit the concept of system vulnerability stack by analyzing the anatomy of fault effects across the abstraction layers and identify the sources of error in well-established transient fault vulnerability evaluation methodologies. By providing insights for all distinct system layers, we showcase that the evaluation should take into consideration all faults that arrive from the underlying hardware as well as their distribution. We additionally quantify the level of error in a PVF estimation that can be attributed to the microarchitecture and the architecture. Current established methodologies fail to capture these aspects and can potentially lead to misleading findings. We experimentally show how PVF estimation can follow opposite (and thus misleading) trends compared to the correct, full-stack Architectural Vulnerability Factor (AVF) estimation and explain the reasons why the higher-level methodologies provide diverging results by showing the anatomy of faults manifestation across the layers. Our experiments are performed on an Armv8 microprocessor model, using different input datasets to thoroughly demonstrate our insights.