Transfer Characteristics Of Device Research Articles

14‐1: A Study on Flexibility Improvement of AMOLED Back Plane and Mask Reduction Process Architecture Using Photo‐sensitive Organic Insulation Films

In this work, the method of patterning inter‐layer deposition (ILD) and passivation layer (PVX) of the AMOLED back plane structure with an organic film was studied. By replacing the inorganic film of SiNx + SiO2 with an organic film Poly‐imide, back plane suitable for flexible AMOLED was secured. It was possible to secure equivalent TFT transfer characteristics of device compared to inorganic inter layer structure by applying low‐temperature buffer and 2nd gate insulator SiNx to the organic inter layer TFT device. Also, VIA + passivation layer 2 mask photo process was replaced with 1 mask photo process using a VIA Half‐tone mask. Both processes were able to secure a process architecture that can be applied to flexible and rollable displays in the future by using photo‐sensitive organic insulation films.

Realization of multi-functional features with ZnO nanosheets/p-Si based electronic device for energy harvesting and memristive switching

This work investigates and reports on the fabrication of a ZnO nanosheets/p-Si heterojunction energy harvester. The proposed nanostructure device exhibits two key functionalities: energy harvesting and memristive characteristics. This allows the device to perform multiple tasks. The ZnO nanostructure sheet was grown using a hydrothermal method. To minimize defect states at the electrode-substrate interface, an optimal phosphorus doping process was employed to achieve minimal substrate sheet resistance. Under an applied pushing force of 0.259 kgf, the energy harvester generated an output voltage and current of 0.5548 V and 44 μA, respectively. The proposed structure produces an output of 24.41 μW at 13 Hz for 2000 cycles. Investigation of the device's transfer characteristics revealed memristive behavior with an on/off ratio of 107. These findings suggest that the multifunctional ZnO nanosheets/p-Si electronic device reported here has promising potential for applications in the Internet of Things (IoT).

Investigation of In0.7Ga0.3As/Ga0.5As0.5Sb-Based Heterojunction TFET with Ferroelectric Gate Dielectric for Performance and Reliability

This paper investigates In[Formula: see text]Ga[Formula: see text]As/Ga[Formula: see text]As[Formula: see text]Sb-based Heterojunction Tunnel Field Effect Transistor with ferroelectric dielectric as stack layer, namely Ferroelectric Dual Material Stacked Double Gate Heterojunction TFET (FDMSDG-HJTFET) for the first time for performance and reliability. Ferroelectric gate dielectric has been inculcated in the device design in addition to the doping of Ga[Formula: see text]As[Formula: see text]Sb in the source region and In[Formula: see text]Ga[Formula: see text]As in the drain region, respectively. The performance of the proposed device is quantified in terms of DC electrical parameters and short channel parameters. The reliability analysis of the proposed device has been carried out in terms of influence of variations of interface trap charges, gate-source overlap length and temperature on the device transfer characteristics. From the simulation results, it can be manifested that the proposed device presents superior DC electrical characteristic and reduced short channel effects as compared to the GaSb/Si Dual Material Stacked Double Gate Heterojunction TFET (GaSb/Si DMSDG-HJTFET), under the influence of group III–V materials and ferroelectric gate dielectric. In addition to this, the proposed device depicts elevated immunity to presence of interface trap charges at the interface, variations in gate-source overlap length and temperature variations as well. The implication of TiO2 as dielectric stack over SiO2 provides exceptional capacitive coupling at the interface and thus assists in the improvement of electrical characteristics of the device by enhancing the electric field. The outcome of the simulation results presents that Ga[Formula: see text]As[Formula: see text]Sb/In[Formula: see text]Ga[Formula: see text]As-based Ferroelectric Dual Material Stacked Double Gate Heterojunction TFET (FDMSDG-HJTFET) can prove to be a competitive alternative for high performance applications with improved reliability. The design and simulation of the proposed device structure has been executed using technology computer-aided design (TCAD) tool.

Simulation of N-type 100V TDMOS Device Characteristics

This paper mainly introduces the TDMOS (Trench Double Diffused MOSFET). Through the simulation of device process parameters, the influence of process parameters on device breakdown characteristics, transfer characteristics, and output characteristics are analyzed from seven aspects from the epitaxial layer thickness, resistivity, implant dose and energy of P body and NSD, trench depth, the spacing and depth of the trench in the terminal structure. Thus, the design standard with a breakdown voltage greater than 100V, a threshold voltage of about 3V, and a resistance lower than 124 mΩ·um2 is reached.

Start-up and heat transfer characteristics of oscillating heat pipe charged with binary partially miscible organic fluid mixtures

The development of highly-efficient, cost-effective and reliable cooling schemes is still a crucial need for prospective applications in energy- and thermal-related areas, and oscillating heat pipes become a promising option due to their simple structures, high performance and versatilities. In this work, an oscillating heat pipe fabricated by a copper flat-plate evaporator and a capillary copper-tube condenser has been developed, and the experimental study was conducted to investigate the start-up and heat transfer characteristics of the heat pipe device using partially miscible HFE7100-ethanol mixtures at mixing ratios in the range of 1:8 to 8:1 due to the advantage of complementary thermo-physical characteristics and the figure of merit with respect to an OHP. Results demonstrate that the oscillating heat pipe performance was mixing ratio dependent, and there existed optimal mixing ratios of 3.5:1 and 3:1 with respect to the start-up temperature/duration and thermal resistance, respectively. At the optimal mixing ratio of 3.5:1, the time and temperature constants related to the startup performance were reduced by 50.5 s and 5.9 °C, respectively, in comparison with that of ethanol. Besides, the thermal resistance of the oscillating heat pipe charged with HFE7100-ethanol mixture was maximally reduced by 35.5% as compared with that of ethanol at an optimal mixing ratio of 3:1. The complementary thermo-physical properties of partially miscible organic fluids as well as the phase transition suppression and easy transition to unidirectional flow circulation account for the performance improvement. Different from single organic mixtures, the binary organic mixtures exhibited distinctive capabilities to improve the oscillating heat pipe performance, and provides a promising candidate for oscillating heat pipe applications.

(Invited) III-Oxide/III-Nitride Heterostructures for Power Electronics and Optoelectronics Applications

Due to their large bandgap, high critical electric field, and availability of high-quality large-size melt-grown bulk substrates, III-oxides including Ga2O3, Al2O3, In2O3, and their alloys have been extensively investigated for a myriad of electronic and optoelectronic applications. Recently, β-Ga2O3 based power electronics, RF transistors, and ultraviolet (UV) photodetectors have been demonstrated with promising performance. However, p-type β-Ga2O3 is still elusive due to high dopant activation energy (>1 eV), large hole effective mass, and hole trapping. This significantly limits the design freedom for β-Ga2O3 devices. Other p-type semiconductors have been proposed to form heterostructures with β-Ga2O3 such as p-NiO, p-Cu2O, and p-type III-nitrides. As popular wide bandgap semiconductors, III-nitrides are promising candidates to form III-oxide/III-nitride heterostructures to enable advanced device structures and new functionalities. Furthermore, III-oxides and III-nitrides can be epitaxially grown on each other with small lattice mismatch (< 5% for GaN and β-Ga2O3) by the industrial standard epitaxial method MOCVD. For example, vertical GaN violet LEDs grown on n-type β-Ga2O3 substrates have been reported. This talk will present our recent work on III-oxide/III-nitride heterostructures in power electronics and optoelectronics.For power electronics, β-Ga2O3/GaN p-n heterojunctions will first be discussed. The heterojunction via mechanical exfoliation shows decent forward rectifying behaviors and thermal stability up to 200 °C but relatively low breakdown voltages (BV). To improve the breakdown capability, we carried out a comprehensive TCAD simulation study to design mesa edge termination for kV-class β-Ga2O3/GaN p-n heterojunctions. It was found that the electric field crowding effect is the main reason for the low BV. Several mesa edge termination structures were investigated such as deeply-etched mesa, step mesa, and p-GaN guard ring. Second, normally-off AlN/β-Ga2O3 field-effect transistors using polarization-induced doping will be discussed. A large two-dimensional electron gas is formed at the AlN/β-Ga2O3 interface due to polarization effects, and p-GaN gate is used to realize tunable positive threshold voltage. The device transfer and output characteristics with different device structures are also studied. For optoelectronics applications, self-powered spectrally distinctive Ga2O3/GaN heterojunction UV photodetectors grown by MOCVD will be discussed. Opposite current polarities are observed under different illumination wavelengths due to different carrier transports, which can be utilized to distinguish different spectra. These results indicate that (ultra)wide bandgap III-oxide/III-nitride heterostructures are a promising platform to enable new device structures and functionalities.

The Short Channel and Quantum Confinement Effects on Transfer Characteristics of Si NWMOSFET Depending on the Gate Length and Temperature

With advancements in nanomaterial synthesis, semiconductor device technology entered a new era with nanotechnology. In fact, quantum effects such as confinement and tunneling have played a significant role in device characteristics. In this work, we have investigated quantum ballistic transport properties of Si nanowire MOSFET (Si NWMOSFET) with 4 nm gate length. Since gate length is shorter than the electron wavelength in our Si NWMOSFET, ballistic transport in one dimension (1D) is expected to be the dominant mechanism for carrier transport. Therefore, the parameters which are crucial for efficient MOSFET operation such as gate length, temperature, gate voltage have been simulated using the density gradient method to present quantum confinement effect on device transfer characteristics. We have found that Si NWMOSFET has an I_on/I_off ratio &amp;gt; 10^8, which is close to ideal value for similar nano MOSFETs. Moreover, due to short channel, intersubband scattering can deteriorate 1D ballistic transport properties of Si NWMOSFET, especially in low temperatures.

Compact model of retention characteristics of ferroelectric FinFET synapse with MFIS gate stack

In this paper, multiple-fin n- and p-channel HfZrO2 ferroelectric-FinFET devices are manufactured using a gate first process with post metalization annealing. The device transfer characteristics upon program and erase operations are measured and modeled. The drift in the transfer characteristics due to depolarization field and charge injection are captured using the shift in the threshold voltage along with time-dependent modeling of vertical field dependent mobility degradation parameters to develop a physical, computationally efficient, and accurate retention model for ferroelectric-FinFET devices. The modeled conductance is incorporated into deep neural network simulation platform CIMulator to analyze the role of conductance drift due to retention degradation, as well as the importance of the gap between high and low conductance states in improving the image recognition accuracy of neural networks.

Numerical research on the solidification heat transfer characteristics of ice thermal storage device based on a compact multichannel flat tube-closed rectangular fin heat exchanger

In this study, a compact ice thermal storage device that combines multichannel flat tube and closed rectangular fins is designed to improve solidification performance. To analyze the heat transfer characteristics and visualize the ice formation process, a numerical model was formulated and solved using enthalpy-porosity method. The temperature distribution, liquid fraction, and ice front evolution were studied during solidification process. The effect of heat transfer fluid on the performance of storage device at different inlet temperatures and flow rates was numerically investigated. Results show that when the inlet temperature was reduced from -3 °C to -6 °C, the ice packing factor increased by 32.2% and the storage power forms a linear relationship with the inlet temperature. When the flow rate was increased from 0.1 m3/h to 0.2 m3/h, the ice packing factor increased by 8.7% but the effect of flow rate was less obvious than the inlet temperature. Furthermore, the heat transfer characteristics of closed rectangular fins were compared with traditional longitudinal fins. We found that the former can achieve more uniform temperature distribution and a higher ice formation rate. The average solidification enhancement ratios of the both are 2.28 and 2.08, respectively, the former being 9.6% higher than the latter.

AlGaN/GaN HEMT pH Sensor Simulation Model and Its Maximum Transconductance Considerations for Improved Sensitivity

In this work, AlGaN/GaN high electron mobility transistor (HEMT) pH sensing simulation model is presented along with the sensitivity analysis to different pH values of an electrolyte by considering charged adsorbates systematically. Investigations were performed by studying the effect of pH values on device transfer characteristics and a smooth operation is observed with good pH resolution. The output current sensitivity is analyzed from both linear and saturation regions highlighting the response obtained at different drain bias. The device intricacies and sensing mechanism is also explained and demonstrated by analyzing the channel conductance, conduction band, potential profile and coupling capacitance along with the charge distribution profile at various interfaces using ATLAS Silvaco device simulation tool. The pH of solution is modelled by incorporating charged adsorbates as interface charge density at oxide-semiconductor interface in HEMT for the first time to best of our knowledge. The voltage sensitivity (S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</sub> ) of 110 mV/pH was observed which is ~2 times beyond Nernst limit of sensitivity (59 mV/pH) and the current sensitivity (S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</sub> ) is 17 mA/mm/pH which is 3 orders higher than silicon based devices. The effects of region of operation is also reported with a maximum upto 8 times higher sensitivity being observed in terms of maximum transconductance (g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ) considerations and a near zero maximum g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> was found to be optimum condition for higher sensitivity operation in reference electrode free configuration. Therefore high sensitive response along with better biocompatibility of AlGaN/GaN HEMT paves its way in next generation biosensing applications.

Research on influence of high and low temperature heat sources for heat transfer characteristics of pulsating heat pipe cold storage device

Research on influence of high and low temperature heat sources for heat transfer characteristics of pulsating heat pipe cold storage device

UV assisted non-volatile memory behaviour using Copper (II) phthalocyanine based organic field-effect transistors

Abstract In this report, we have demonstrated the optical non-volatile memory characteristics using CuPc OFET. The memory operation was comprehensively demonstrated with different programming conditions. It was found that the programming of CuPc OFET with an electric pulse at the gate terminal under UV-light photo-illumination compared to other programming conditions, could substantially increase the memory window due to massive charge trapping in the polymer electret layer, which causes shift in the device transfer characteristics from low-conduction state (“OFF state”, or logic 0) to high conduction state (“ON state”, or logic 1) at VGS = 0V. From device operation at −50V, a memory window of greater than 45V could be achieved by applying a programming voltage of +70 V at the gate terminal under UV-light photo-illumination. Moreover, it was completely erased by applying −100 V at the gate terminal in dark.

Dual Metal Double Gate Ge-Pocket TFET (DMG-DG-Ge-Pocket TFET) with Hetero Dielectric: DC &amp; Analog Performance Projections

This work exclusively illustrates dual-metal double gate Ge pocket tunnel field effect transistor (DMG-DG-Ge pocket TFET) with hetero gate dielectric. This structure includes dual-metal gate and hetero-dielectric as well. Extensive TCAD simulation analysis is carried out to illustrate how the device transfer characteristics changes in different regions with respect to various parameters such as, the work-function of tunneling gate and auxiliary gate variations, lengths ratio of tunneling gate and auxiliary gate, and the dielectric constants of homo/hetero dielectrics involved. Here, optimization of dual metal gate work-function is done along with dual gate metal length ratio. To optimize the device behavior hetero gate dielectric HfO2 and SiO2 are considered over the source-channel interface and channel-drain interface, respectively. The enhanced device transfer characteristics obtained are explained and verified with the energy band diagram and tunneling length. The reported device structure achieves ION/IOFF = 5.05 × 1011 and sub-threshold slope (SS) as 15.9425 mV/decade along with the reduced ambipolar current. An increase in ION/IOFF ratio by the order of four as compared to Ge-pocket TFET, is reported with reasonably high ON current for sub 0.5 V supply. This enables the device for low power applications. In addition to this, for the complete analog and RF characterization of the proposed device structure, transconductance, parasitic capacitance, cut-off frequency, intrinsic delay, energy-delay product, transconductance generation factor etc. are also illustrated in detail here. Further, the energy efficiency of the device is also analyzed and justifies for its low power high-speed applications.

Study on uniaxial stress intensity of MOS channels along different crystal planes induced by SiN-film

The process conditions for depositing SiN film on small-sized MOS along different crystal face channels to introduce stress are the same. However, since the elastic stiffness coefficient of channel Si material is anisotropic, the stress intensity introduced in small-sized MOS channels along different crystal planes is different. It is necessary to consider it while designing and manufacturing small-sized strained MOS. In this paper, the uniaxial strained Si PMOS and NMOS with 40 nm channel along different crystal faces were produced by compressive stress and tensile stress SiN film respectively. Quantitative results of uniaxial stress intensity of MOS channel along different crystal planes induced by the same process SiN films were obtained by measuring device transfer characteristics and corresponding theoretical calculations. The results indicate that, for strained NMOS induced by the tensile stress SiN film, (100) and (110) crystal plane channels are subjected to 0.8 GPa and 1.6 GPa tensile stress; for strained PMOS induced by the compressive stress SiN film, (100), (110), and (111) crystal plane channels are subjected to compressive stresses of 1.1 GPa, 0.8 GPa and 1.6 Gpa, respectively.

Time-resolved electrical characteristics of ferroelectric-gated fully depleted silicon on insulator devices

The performance of fully depleted silicon on insulator (FDSOI) device and ferroelectric-gated FDSOI (FE-FDSOI) device are investigated for various gate voltage sweep rates. Regardless of the gate voltage sweep rates, the input transfer characteristics of the baseline FDOSI device are not varied. On the contrary, it was observed that the hysteresis width of the FE-FDSOI device is affected by the gate voltage sweep rates. As the gate voltage sweep rate decreases, the ratio of ferroelectric remnant polarization to coercive voltage (Pr/Vc) increases, so that the magnitude of the ferroelectric negative capacitance (|CFE|) increases. This affects hysteresis condition of the FE-FDSOI device, therefore, the hysteresis width of the FE-FDSOI device decreases as the gate voltage sweep rate decreases. According to the results, it is suggested that voltage sweep rate be decreased to decrease the hysteresis width of FE-FDSOI device.

A resonant tunneling field effect transistor utilizing silicene nanoribbon

In this paper, we propose a resonant tunneling field effect transistor based on silicene nanoribbons with different ribbon widths. In this case, due to the variation in the energy gap of silicene nanoribbon at different ribbon widths, a quantum well structure is formed and discrete confined states appear. By adjusting the gate voltage in the channel region, energy levels can be adjusted in such a way that carriers can be transported through the tunneling process. We show that the energy gap of this structure is changed via two parameters of the electric field and ribbon width. Furthermore we examine the effect of these parameters, as well as the channel length on the device transfer characteristics and the ratio of Ion/Ioff. We also observe that the output characteristic is step-like and it rises by increasing the drain voltage. Also, we study the effect of channel length and different gate voltages on the output characteristics.

High-k Fluoropolymer Gate Dielectric in Electrically Stable Organic Field-Effect Transistors.

A detailed study of a high-k fluoropolymer gate dielectric material, poly(vinylidene fluoride- co-hexafluoropropylene) [P(VDF-HFP)], is presented as a guide to achieve low operational voltage and electrically stable device performance. The large dipole moment of C-F dipoles in P(VDF-HFP) is responsible for its high dielectric constant as well as its potentially ferroelectric behavior that must be minimized to avoid hysteretic current-voltage characteristics. A range of material grades and processing conditions are explored and are shown to have a significant effect on the degree of hysteresis observed in device-transfer characteristics. The percentage of HFP monomer in the P(VDF-HFP) dielectric has an effect on gate-dependent mobility induced by disorder at the semiconductor-dielectric interface. Most importantly, we present the considerations that must be made to achieve optimal performance in multiple device architectures of organic field-effect transistors when using P(VDF-HFP) as a dielectric layer.

Graphene‐Based Electronic Immunosensor with Femtomolar Detection Limit in Whole Serum

AbstractPurely electronic diagnostic devices that are sensitive to biomolecules' intrinsic charge present a very attractive platform for point‐of‐care (PoC) applications, since they can operate under label‐free conditions. In this report, a graphene‐based electrolyte‐gated field‐effect transistor is developed as an immunosensor capable of sensitive analyte detection, even in the complex environment of physiological samples. The coimmobilization of an antibody fragment (F(ab′)2) and polyethylene glycol on the graphene surface allows for a highly sensitive and selective detection of a protein analyte, with a limit of detection in the low femtomolar range, both in high ionic strength buffer and undiluted serum. Multiparametric analysis of the device's analyte‐dependent electronic response shows that the mechanism behind this very sensitive detection cannot be explained by a commonly reported electrostatic gating effect. Rather, the observed combination of charge neutrality point shifts and asymmetric mobility changes are attributed to the modulation of scattering by charged impurities, which seem to dominate the device's transfer characteristics. Furthermore, the reproducibility of the normalized signal response obtained from several different devices shows that this graphene‐based immunosensor is capable of direct and quantitative measurements of protein analytes in untreated serum, imperative for diagnostic tools geared toward PoC applications.

Understanding hydrogen and nitrogen doping on active defects in amorphous In-Ga-Zn-O thin film transistors

This work analyses the physics of active trap states impacted by hydrogen (H) and nitrogen (N) dopings in amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) and investigates their effects on the device performances under back-gate biasing. Based on numerical simulation and interpretation of the device transfer characteristics, it is concluded that the interface and bulk tail states, as well as the 2+ charge states (i.e., acceptors VO2+) related to oxygen vacancy (VO), are neutralized by the H/N dopants incorporation via an experimental plasma treatment. Moreover, the simulation reveals that an acceptor-like defect VOH has been induced by the H doping, to support the observed additional degradation of device subthreshold slope. Superior stability of the optimized a-IGZO TFTs under a proper amount of H/N doping is demonstrated by the decreased density of VO-related defects in simulation, where hole (VO0 donor) and electron trapping (Oi acceptor) occurs during the negative or positive bias stresses. This work benefit lies in an in-depth systematic understanding and exploration of the effects of the incorporation of the H and N dopants into the a-IGZO film for the TFTs improvement and optimization.

Electric Double Layer Doping of WSe2 Field-Effect Transistors Using a Monolayer Electrolyte

Electric double layer (EDL) doping using a polymer electrolyte or ionic liquid is a common technique to explore transport in two-dimensional (2D) materials. The doping relies on the formation of an EDL due to the accumulation of mobile ions at the interface between an electrolyte and a 2D semiconductor. The induced image charge yields large capacitance densities (1-10 μF/cm2) and sheet carrier densities (~1014 cm-2) in 2D crystal field-effect transistors (FETs).1 Our group has developed a monolayer electrolyte that is a single molecule thick and can electrostatically dope the surface of 2D semiconductors.2 The monolayer electrolyte has several advantages over liquid-phase electrolytes because it is solid state, bistability has been demonstrated,2 and DFT calculations predict a low switching voltages (sub-volt) at fast speeds (sub-ns).3 We have demonstrated EDL doping on graphene2 and MoS2 using the monolayer electrolyte. Bistability, state retention and a sheet carrier density of 3.2×1012 cm-2 have been demonstrated. In this study, WSe2 is selected as the 2D channel because it is ambipolar with a sizable bandgap (1.4 eV), large on/off ratio (> 106) and high carrier mobility (~140 cm2V-1s-1).4 The monolayer electrolyte consists of cobalt crown ether phthalocyanine (CoCrPc) and lithium perchlorate (LiClO4) (Fig.1 (a)). CoCrPc is an atomically thin and electrically insulating molecule (band gap ~1.34 eV) that can lie flat on a 2D surface.5 It includes four crown ethers, and each of them can solvate one Li+.6 An ordered array of CoCrPc can be deposited on a 2D material by drop-casting and annealing.5 Back-gated WSe2 FETs were fabricated by electron beam lithography (EBL), and the monolayer electrolyte was deposited on the surface of the WSe2 FETs by drop-casting and annealing. The WSe2 channel surface was cleaned by contact-mode AFM to remove e-beam resist residue before electrolyte deposition to avoid interference to the packing arrangement of the monolayer electrolyte. The quality of the cleaning is confirmed by AFM topography and surface roughness measurements; the roughness after the cleaning equals the value of freshly exfoliated flakes (Rq ~0.22 nm) (Fig.1 (c) and (d)). The cleaning does not deteriorate the back-gated device performance, as indicated by transfer characteristics after the AFM cleaning (Fig.1 (b), no monolayer electrolyte). The device transfer characteristics before and after doping with the monolayer electrolyte will be presented, along with our work on top-gating the devices using h-BN and graphene to create an all-2D EDL FET. References Kim, Se Hyun, et al. Advanced Materials 25.13 (2013): 1822-1846.Xu, Ke, et al. ACS nano (2017).Wang, Wei-Hua, et al. Solid State Ionics 301 (2017): 176-181.Fang, Hui, et al. Nano letters 12.7 (2012): 3788-3792.Lu, H., et al. The Journal of Physical Chemistry C 119.38 (2015): 21992-22000.De, S., et al. Journal of Molecular Structure: THEOCHEM 941.1 (2010): 90-101. ACKNOWLEDGEMENTS: This work was supported by NSF-ECCS/GOALI 1408425 and by the Center for Low Energy Systems Technology (LEAST), a STARnet Semiconductor Research Corporation program sponsored by MARCO and DARPA. Figure 1