Transfer Characteristics Of Device Research Articles

A Behavioral Model for High Ge Content in Si/Si1-xGex Multi-Quantum Well Detector

This paper presents a behavioral model for a Si/Si1− x Ge x multi-quantum well (MQW) detector that predicts device characteristics to investigate the effect of increasing Ge content in Si/Si1− x Ge x MQW. The modeling approach in this paper is based on a physical instead of empirical approach, which allows to obtain a predictive behavioral analysis of high Ge content with only a few fitting parameters. The model is used to simulate device transfer characteristics with respect to various amounts of Ge content used for Si1− x Ge x layer in MQW. The simulation results of the proposed model are validated with the experimental data. The simulated and the experimental data are consistent over a wide range of Ge content varied from 30% up to 50%. The primary objective of this paper is to optimize Ge content in the Si/Si1− x Ge x MQW detector to achieve desired thermal sensitivity measured in terms of temperature coefficient of resistance for a potential microbolometer application. This is the first study in the literature to develop such a highly predictive behavioral model of a Ge-enriched Si/Si1− x Ge x MQW. The study also presents the effect of including the carbon delta layers at the Si/Si1− x Ge x heterointerface on the device transfer characteristics. The effect of Ge content on the overall noise is also investigated by the noise characterization of the test devices.

(Invited) High Power Diamond Devices with 2-D Transport Channels

Diamond transistors with surface 2D conduction channels are projected to be radiation hard with respect to neutrons. However, ionizing radiation hardness may be a problem due to the disruption of the 2D hole concentration. In this paper, the processing of three terminal devices with 2D surface conducting channels is presented as well as analysis of device transfer characteristics. This paper addresses the fabrication, radiation induced defects and device characteristics of microwave power field effect transistors (FET) built on 1) high quality diamond surfaces exploiting the 2 dimensional surface conductivity, and 2) the surface two dimensional “hydrogen terminated” conduction layer in diamond single crystals grown by CVD. Diamond is an ultra-wide bandgap semiconductor material that exhibits a number of ideal properties for future power and RF electronics applications beyond the current generation of SiC- and GaN-based technology. These properties include a bandgap of 5.5 eV, a high breakdown field (>10 MV/cm), high theoretical room-temperature carrier mobilities (>3800 cm2/V*sec), extremely high thermal conductivity (>22 W/cm*K), and excellent mechanical and thermal stability in vacuum. However, diamond doping is difficult, as the activation energies for typical dopants (B, P) exceed 0.37 eV and lead to very low dopant activation levels.[3] This drawback of dopant activation efficiency has been, in part, mitigated by two-dimensional conductivity found in hydrogen-terminated diamond surfaces. Hydrogen-termination (usually accomplished via exposure to hydrogen plasma) has been found to create a C-H surface dipole layer that reduces the carrier ionization energy by nearly 1.5 eV. Adsorbed species, such as atmospheric H2O, NO2, or intentionally-introduced passivation species contact this dipole layer, and together generate a two-dimensional hole gas (2DHG) with 1013-1014 holes/cm2 carrier density several nanometers below the diamond surface. Hydrogen-terminated diamond has been used as the basis for metal-semiconductor field effect transistors (MESFETs) and metal-oxide-semiconductor field effect transistors (MOSFETs) hydrogen-terminated diamond. Both unpassivated and passivated surface conduction devices have been fabricated. In the case of unpassivated devices, exposure to air (and thus atmospheric H2O) causes the devices to exhibit sheet charge densities in the 1013 holes/cm2 range.[1] MESFETs typically rely on Au metal for Ohmic contacts and Al metal for Schottky contacts to the hydrogen-terminated diamond. These devices have been normally-on devices, with threshold voltages around between -1V to +1V, depending on device dimensions.[1-4] MOSFETs fabricated using atomic layer deposited (ALD) oxides such as Al2O3 have been fabricated with either normally-off or normally-on behavior, depending on thermal history. Annealing of these devices at 180°C caused the devices to switch from normally-on to normally-off, with threshold voltages again in the range of ±1V range; the change was likely due to the removal of adsorbed species in the unpassivated diamond surfaces between the source, gate, and drain regions in the device, causing a reduction in the 2DHG sheet carrier density.[4] The diamond materials and surface preparation supplied by Euclid Techlabs using proprietary processes to produce defect free, ultra-smooth (Sa ~ 0.2 nm) diamond surfaces and buried boron ‘delta doped’ CVD layers. Euclid techlabs has demonstrated the delta doped transport channels in Diamond have mobilities in excess of 700 cm2/V sec. Device design and process science development was carried out within the facilities of the UMD NanoCenter and the NanoFab Lab. Radiation testing has been carried out at the radiation facilities of the University of Maryland. Device electrical performance and characterization has been carried out. We perform baseband noise, as well transconductance/output resistance dispersion characterization of 2D Surface Channel Diamond FETs fabricated under different processes and having different geometry and designs in order to identify device defects and their reliability and their susceptibility to radiation effects. The impact of the various types of noise on device defect and radiation hardness will be reported. Materials characterization techniques including Raman spectroscopy (strain, sp2 vs sp3 bonding), FTIR, and SIMS. Common diamond point defects are characterized by photoluminescence and FTIR.

Operational frequency degradation induced trapping in scaled GaN HEMTs

Cut-off frequency increase from 12.1GHz to 26.4GHz, 52.1GHz and 91.4GHz is observed when the 1μm gate length GaN HEMT is laterally scaled down to LG=0.5μm, LG=0.25μm and LG=0.125μm, respectively. The study is based on accurately calibrated transfer characteristics (ID-VGS) of the 1μm gate length device using Silvaco TCAD. If the scaling is also performed horizontally, proportionally to the lateral (full scaling), the maximum drain current is reduced by 38.2% when the gate-to-channel separation scales from 33nm to 8.25nm. Degradation of the RF performance of a GaN HEMT due to the electric field induced acceptor traps experienced under a high electrical stress is found to be about 8% for 1μm gate length device. The degradation of scaled HEMTs reduces to 3.5% and 7.3% for the 0.25μm and 0.125 gate length devices, respectively. The traps at energy level of ET=EV+0.9eV (carbon) with concentrations of NIT=5×1016cm−3, NIT=5×1017cm−3 and NIT=5×1018cm−3 are located in the drain access region where highest electrical field is expected. The effect of traps on the cut-off frequency is reduced for devices with shorter gate lengths down to 0.125μm.

(Invited) High-Yield Reconfigurable Silicon and Germanium Nanowire Transistors and Compact Logic Circuits

Semiconductor nanowire transistors are considered potential successors of finFETs providing the ultimate miniaturization capabilities of MOS transistors and thus targeting ultimate circuit complexity and performance. A promising perspective for further advancement beyond classical CMOS scaling is to exploit functionality enhancement of nanowire transistors. Several nanowire based multi-gated device concepts known as reconfigurable field effect transistors (RFETs) or polarity control FETs that combine multi-functionality with the inherent advantages of silicon nanowires are being currently evaluated [1-4]. These multi-terminal devices merge unipolar n- and p- FET switching characteristics from the same device as selected simply by an electric signal and without the need for doping enabling complementary CMOS operation with a single kind of transistor. RFETs make use of two sharp metal-NiSi2 / intrinsic-silicon interfaces with individual gates for the selective injection of electrons and holes into the channel region [5]. Additional independent steering gates can be integrated to further enhance functionality without comprising on-conductance [6]. In order to allow complementary circuit operation symmetry in the p- and n-type I-Vcharacteristics is mandatory. To this end, we show both experimentally [7] and by device simulations [8] that the application of radial compressive strain to <110> oriented silicon nanowires is able to align the injection efficiency of electrons and holes for diverse nanowire geometries. Full swing complementary operating circuits such as inverters [7] and compact six transistor cells yielding NAND, NOR and minority functions as demonstrated with symmetric RFETs and 3XOR gates with only 8 transistors vs. 24 with CMOS [6,7,10,11]. These gates build the basis for arithmetic building blocks such as one-bit adders with substantially lower transistor count reducing critical pathes, delay and power consumption as compared to conventional CMOS [6]. The RFET concept has been recently successfully transferred to a parallel nanowire technology [12,13] principally enabling to build low operation power circuits and sensors on plastic substrates. Finally, we show that germanium based RFETs improve the individual device performance and to reduce dynamic power consumption without comprising static power consumption. Figure caption: a) Schematic of reconfigurable nanowire FET (RFET) encompassing intrinsic Si nanowire channel and two independently gated Si / NiSi2 junctions. b) Oxide induced compressive stress in Si nanowire core required to adjust electron and hole currents: TEM cross section of nanowire channel with overlay of computed mechanical strain distribution. c) SEM image of abrupt Si / NiSi2 junction. d) SEM of symmetrically operating RFET with electrical device symbol. e) Symmetric p- and n-program I-V transfer characteristics of device depicted in d). f) SEM of inverter built of two RFETs within a single nanowire. g) Measured inverter transfer characteristic with supply voltage of Vdd = 2V showing low operation power complementary behavior and full swing output. Propagation delay for scaled structure and for different fanouts. Output of reconfigrable NAND/NOR/Minority 6-transistor cell, shows reconfiguration at runtime (mixed -mode computations). h) High-yield printed silicon nanowire FETs encompassing ~ 1xE3 parallel nanowires with meander source/ drain / gate structure. Technology is compatible with flexible plastic substrates.

Elevated Temperature Operation of 4H-SiC Nanoribbon Field Effect Transistors.

We fabricated 4H-SiC nanoribbon field effect transistors (FETs) of various channel thickness (tch) of 100~500 nm by a "top-down" approach, using a lithography and plasma etching process. We studied the dependence of the device transfer characteristics on the channel geometry. This demonstrated that fabricated SiC nanoribbon FETs with a tch of 100 nm show normally-on characteristics, and have a threshold voltage of -12 V, and a maximum transconductance value of 8.8 mS, which shows improved drain current degradation of the SiC nanoribbon FETs with tch = 100 nm at elevated temperature. This can be attributed to the improved heat dissipation, enhanced channel mobility, and together with widening of effective channel thickness depletion induced.

An Organic Field-effect Transistor with an Extended-gate Electrode Capable of Detecting Human Immunoglobulin A.

We herein report on the development of an extended-gate type organic field-effect transistor (OFET)-based immunosensor for the detection of human immunoglobulin A (IgA). The titration results of IgA exhibited shifts in the transfer characteristics of the OFET sensor device with increasing IgA concentration. A linear detection range from 0 to 10 μg/mL was realized with a detection limit of 2.1 μg/mL, indicating that the OFET-based immunosensor can be potentially applied to the monitoring of infectious diseases and psychological stress in daily life.

A Novel Backside Gate Structure to Improve Device Performance

AlGaN/GaN HEMTs have gained more attention recently because of the superior mobility (~1400 cm2/V-s) and high breakdown voltage. However, the reported breakdown voltage (~2000V at Lds=40µm) was still below GaN limit. The reason might be due to surface traps, defects in GaN buffer layer, etc. Methods to improve breakdown voltage include acceptor doping in buffer layer, insulator passivation or field plate over dielectric passivation. In this paper, we propose a new structure, which opened a via through the substrate as a backside gate and a field plate, and demonstrate the improvement of device performance such as transport characteristics and breakdown voltage. The HEMT structures consisted of a 25 nm AlGaN barrier layer, a 0.8 µm C doped GaN buffer layer, a 1.4µm AlGaN transition layer and a thin AlN nucleation layer on 300µm Si substrate. HEMT fabrication began with Ti/Al/Ni/Au Ohmic metallization and rapid thermal annealing in N2 at 825ºC. Isolation was accomplished by use of multiple energy N+ implantations. After implantation, the devices were passivated with 70-nm-thick SiNx by PECVD at 300ºC. Gate definition was achieved by patterning the gate and selectively removing the SiNx layer. The contact windows to the Ohmic contact pads were also opened simultaneously as defining the gate. After SiNx etching, wider gate patterns and Ohmic contact pads were opened. Ni/Au-based gate metallization was deposited on the gate and Ohmic contact pads simultaneously. The devices were then passivated with another 400-nm SiNx layer at 300ºC. The contact windows were opened by dry etching. The LDS was 4 µm. The LG was 0.45 and WG was 100 µm, respectively. There was an additional metal deposition for source field plate (FP). It was connected to the source and extended by 1 µm out over the gate to the gate-to-drain region. Above process flows are our standard process flow for reference. For our new structure, to drill via holes on the backside of the devices, the wafers were first polished to 150µm. Photoresist AZ9260 were used to pattern the via holes on the backside of the samples and aligned to the front side by Aligner MJB3. The high aspect ratio of the via holes were fabricated by BOSCH process. After forming via holes, Ti/Au was sputtered to form the backside gate (BG). Figure 1 showed effect of backside voltage (VBG) to drain I-V characteristics. As shown in Figure 1, the drain saturation current decreased and the channel resistance became higher after applying VBG at -10 V. Also, the drain current at pinch off region get decreased. This is due to the introduction of another depletion region from the backside of the device. In other words, the BG provided an additional control of the device, which made the device more robust. Figure 2 showed the transfer characteristics of device with and without applying VBG. As shown in Figure 2, both of the on current and off current became lower. Besides, the sub-threshold slope became steeper after applying -10 V at the BG, which meant better modulation of the device. Due to the better pinch off of the device, the breakdown voltage (VBD) was significantly improved. Table 1 showed the summary of the effect of VBG. As shown in TABLE 1, although IDS was slightly decreased, but the more reduction of gate current improved on/off ratio for one order, sub-threshold swing from 204 to 137 mV/dec, and VBD for 40%. These improvements were all achieved because of the backside gate. Besides applying VBG to improve VBD, the BG could be used as a FP, too. Studies have shown that FP can redistribute the electric field, and thus increase the VBD. In this study, we demonstrate the similar result. When connecting the BG to front-side gate, the VBD could be increased around 8 % as shown in Figure 3. When connecting the BG to front-side source, VBD didn’t have noticeable improvement. The reason that source FP didn’t have obvious effect in our study might be the existence of front-side FP. On the other hand, drain FP actually decrease the VBD. For drain FP, the backside FP was at positive bias. This positive bias along with the front-side positive bias would generate hot electrons and enhance the tunneling. In summary, VBD could be improved by simply connecting the backside gate to front-side gate. In conclusion, we demonstrate a new structure for AlGaN/GaN HEMT. This structure could improve the on/off ratio, sub-threshold swing, and breakdown voltage. It is worth to see if it could improve short channel effect, self-heating effect, or current collapse. Figure 1

Influence of heavy ion irradiation on DC and gate-lag performance of AlGaN/GaN HEMTs**Project supported by the National Natural Science Foundation of China (Grant No. 61204112).

AlGaN/GaN high electron mobility transistors (HEMTs) were irradiated by 256 MeV 127I ions with a fluence up to 1×1010 ions/cm2 at the HI-13 heavy ion accelerator of the China Institute of Atomic Energy. Both the drain current Id and the gate current Ig increased in off-state during irradiation. Post-irradiation measurement results show that the device output, transfer, and gate characteristics changed significantly. The saturation drain current, reverse gate leakage current, and the gate-lag all increased dramatically. By photo emission microscopy, electroluminescence hot spots were found in the gate area. All of the parameters were retested after one day and after one week, and no obvious annealing effect was observed under a temperature of 300 K. Further analysis demonstrates that swift heavy ions produced latent tracks along the ion trajectories through the hetero-junction. Radiation-induced defects in the latent tracks decreased the charges in the two-dimensional electron gas and reduced the carrier mobility, degrading device performance.

On-line electrodialytic matrix isolation for chromatographic determination of organic acids in wine

Chromatographic determination of organic acids is widely performed, but the matrix often calls for lengthy and elaborate sample preparation prior to actual analysis. Matrix components, e.g., proteins, non-ionics, lipids etc. are typically removed by a combination of centrifugation/filtration and solid phase extraction (SPE) that may include the use of ion-exchange media. Here we report the quantitative electrodialytic transfer of organic acids from complex samples to ultrapure water in seconds using cellulose membranes modified with N,N-dimethylaminoethyl methacrylate, which essentially eliminates the negative ζ-potential of a regenerated cellulose membrane surface. The transfer characteristics of the ion transfer device (ITD) were evaluated with linear carboxylic acids. While the ion transfer efficiencies may be affected by the acid dissociation constants, in most cases it is possible to achieve quantitative transfer under optimized device residence time (solution flow rate) and the applied voltage. In addition, the transfer efficiency was unaffected by the wide natural variation of pH represented in real samples. The approach was applied to organic acids in various samples, including red wine, considered to represent an especially difficult matrix. While quantitative transfer of the organic acids (as judged by agreement with standard pretreatment procedures involving SPE) was achieved, transfer of other matrix components was <5%. The processed samples could then be chromatographically analyzed in a straightforward manner. We used ion exclusion chromatography with direct UV detection; in treated samples; there was a dramatic reduction of the large early peaks observed compared to only 0.45μm membrane filtered samples.

Effects of substrate leakage and drain-side thermal barriers in In0.53Ga0.47As/GaAs0.5Sb0.5 quantum-well tunneling field-effect transistors

The device leakage current and the ON-state characteristics of In0.53Ga0.47As/GaAs0.5Sb0.5 quantum-well tunneling field-effect transistors (QWTFETs) are examined on the basis of temperature-dependent measurements. Different from commonly observed Shockley–Reed–Hall (SRH) recombination in the OFF-state, substrate leakage is identified as the source of OFF-current, which limits the steepness of the device transfer characteristics. In addition, analysis of the TFET operation in the linear regime reveals a current barrier due to an ungated region near the drain, which accounts for the unexpected parasitic resistance and current saturation at low temperatures. This barrier can be eliminated by reducing the gate-to-drain distance, as illustrated by device simulations. The applied methodology provides a design guideline for the gate-to-drain alignment tolerance in TFETs.

Threshold voltage extraction in Tunnel FETs

This article proposes two possible extrapolation-type methods to extract the threshold voltage of Tunnel Field Effect Transistors (TFETs). The first one, which we call the “CTR method,” makes use of the drain Current-to-Transconductance Ratio function. As this method requires differentiating the drain current with respect to the gate voltage, it is blurred by the amplified effect of measurement noise when applied to real device transfer characteristics. To avoid this effect, a second method is also proposed that uses integration of the drain current with respect to gate voltage instead of differentiation. This second method, which was named “H1 method” when it was originally applied to non-crystalline inversion mode MOSFETs, produces comparable results to those obtained from the CTR method, but it has the advantage of inherently reducing the effect of measurement noise by virtue of the low-pass filtering capacity of integration. Both methods are based on defining threshold voltage as the gate voltage axis intercept of the linearly extrapolated strong conduction behavior of either CRT or H1 functions. This is made possible by approximating the drain current in the strong conduction region of the TFET’s transfer characteristics by a monomial function of the gate voltage. Both methods are illustrated and compared by applying them to measured transfer characteristics of experimental Fin-type TFETs.

Current degradation due to electromechanical coupling in GaN HEMT's

In this work we first report on a theoretical model which provides the gate voltage dependence of the piezoelectric polarization charge in GaN HEMT devices. The model utilizes a generalization of Gauss' law, imposing constraints on the electric displacement vector D. The constraint on D is given by the continuity of the perpendicular component of the displacement vector across an interface. Poisson's equation is then solved across various layers under proper boundary conditions for the applied bias. The piezoelectric polarization charge is reduced due to the electromechanical coupling compared to the uncoupled case. Under high sheet electron densities, the correction in the piezoelectric polarization charge is also lower due to smaller electric fields. The theoretical model is then incorporated in the particle-based device simulator and device transfer and output characteristics are calculated without and with the bias dependent polarization charge. We find that percentage change in drain current increases with larger negative bias on the gate, due to the larger vertical electric fields.

A Simulation Study on Process Sensitivity of a Line Tunnel Field-Effect Transistor

A process sensitivity study of a steep subthreshold swing line tunnel field-effect transistor is presented for the first time using 2-D quantum-mechanical device simulations. The impact of various process parameters on the device transfer characteristics is presented with the help of process splits. A study of the thermal budget also shows that an increase in epitaxial growth thermal budget degrades the device performance by increasing the tunneling onset voltage <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TON</sub> and the off-current. Through process simulation and Plackett-Burman design of experiment (PB-DOE), the epitaxial layer thickness of the channel was identified as the most critical parameter in device processing. A thickness variation from 2 to 3 nm in the highly ( 7 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">19</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> ) doped epitaxial was found to cause ~ 500-mV change in the tunneling onset voltage. It was found that an increase in doping concentration in the epitaxial layer to reduce quantum confinement effects will lead to an increase in the sensitivity of the device to the thickness of the epitaxial layer. A thicker epitaxial layer (5-6 nm) with lower doping concentration is recommended for reduced epitaxial layer variation sensitivity.

Gate‐Induced Modification of Water Adsorption on Dielectrics Probed by EFM and Carbon Nanotube FETs

Humidity plays an important role in molecular electronics. It facilitates charge movement on top of dielectric layers and modifies the device transfer characteristics. Using two different methods to probe temporal charge redistribution on the surface of dielectrics, we were able to extract the surface humidity for the first time. The first method is based on the relaxation time constants of the current through carbon nanotube field-effect transistors (CNTFETs), and the second is based on electric force microscopy (EFM) measurements. Moreover, we found that applying external gate biases modifies the surface humidity. A theoretical model based on dielectrophoretic attraction between the water molecules and the substrate is introduced to explain this observation, and the results support our hypothesis. Furthermore, it is found that upon the adsorption of two to three layers of water the surface conductivity saturates.

Numerical simulations of N-type CdSe poly-TFT electrical characteristics with trap density models of Atlas/Silvaco

In this work, the two-dimensional numerical simulations of N-type CdSe polycrystalline (poly-) TFTs’ electrical characteristics are performed using a physically based device simulator Atlas/Silvaco. The analytical expressions of trap density models for acceptor- and donor-like traps are defined for poly-CdSe thin film material. The parameters of trap density distributions are extracted based on fitting the simulated and measured results of fabricated CdSe poly-TFTs. It is shown that the discrete numerical method used for trapped charge evaluation in Atlas gives excellent agreement between simulated and measured characteristics, while the continuous numerical approach is less accurate. In addition, the interface trapped charge causing hysteresis in device transfer characteristics is estimated from simulations and shown to increase almost exponentially with the increase of density of shallow tail states.

Stability of Zinc Oxide Thin-Film Transistors

In this paper, the construction and stability of thin-film transistors (TFTs) with ZnO as active layer are investigated. The bottom-gated ZnO TFTs exhibit n-channel enhancement mode behavior, including an on/off current ratio of 2.4×1E7, a low off-current value in the order of pA, a field effect mobility of 1.8cm*cm/V•s. The threshold voltage shift in positive direction with increasing the channel length is clearly observed. The application of positive and negative stress results in the device transfer characteristics shifting in positive and negative direction. The stressed devices show a logarithmic time-dependent threshold voltage shift and recover to near-original characteristic without any annealing

Read Characteristics of Independent Double-Gate Poly-Si Nanowire SONOS Devices

This paper investigates the read operation of poly-Si nanowire silicon-oxide-nitride-oxide-silicon devices with independent double-gate (IDG) configuration. The device features oxide-nitride-oxide (ONO) stack as the charge storage medium in one of the two gated sides with pure oxide in the other. Owing to the IDG feature, the shift in the device's transfer characteristics due to a change in the amount of storage charges can be sensed with two different modes, which have one of the two gates applied with a sweeping bias (driving gate) and the other with a fixed bias (control gate). Our analysis and experimental data show that a larger memory window is obtained when the gate of the ONO side is used as the driving gate. Moreover, the memory window of this mode is essentially independent of the bias applied to the control gate. Based on this finding, a novel Flash structure featuring IDG cells with a common control gate is proposed.

Voltage Transfer Characteristics in GaAs-Based Three-Branch Nanowire Junctions Controlled by Schottky Wrap Gates

Nonlinear voltage transfer characteristics in GaAs-based three-branch nanowire junctions (TBJs) controlled by Schottky wrap gates (WPGs) are investigated by characterization of the gate voltage and size dependences in detail. WPGs squeezed the nanowires only in the node portion and modulated the curve only in the low-input-voltage region. When the entire nanowire was narrowed geometrically, the voltage transfer curve became abrupt in a wide voltage range. On the other hand, the nanowire length affected only the curve in the high-input-voltage region. These results indicate that the voltage transfer characteristics of the WPG-controlled TBJ device in the low- and high-voltage regions are controlled by the junction node with WPGs and the end of the positively biased nanowire, respectively. The observed behaviors can be understood in terms of a surface-potential-induced field domain model.

Importance of the Gate-Dependent Polarization Charge on the Operation of GaN HEMTs

We investigate the influence of the gate-voltage dependence of the polarization charge on the electron sheet charge density in the channel and how it reflects on the device transfer and output characteristics in GaN HEMTs. We find that a 10% increase in the polarization charge is needed to match the experimental data when the gate-voltage dependence of the polarization charge is included in the theoretical model. This information is important for calibration in commercial device simulators and for better understanding of the quality of the GaN/AlGaN interface.

Carbon nanotube thin film transistors based on aerosol methods

We demonstrate a fabrication method for high-performance field-effect transistors(FETs) based on dry-processed random single-walled carbon nanotube networks(CNTNs) deposited at room temperature. This method is an advantageous alternativeto solution-processed and direct CVD grown CNTN FETs, which allows usingvarious substrate materials, including heat-intolerant plastic substrates, and enablesan efficient, density-controlled, scalable deposition of as-produced single-walledCNTNs on the substrate directly from the aerosol (floating catalyst) synthesisreactor. Two types of thin film transistor (TFT) structures were fabricated toevaluate the FET performance of dry-processed CNTNs: bottom-gate transistors onSi/SiO2 substrates and top-gate transistors on polymer substrates. Devices exhibited on/off ratios up to105 and field-effectmobilities up to 4 cm2 V−1 s−1. The suppression of hysteresis in the bottom-gate device transfer characteristics by meansof thermal treatment in vacuum and passivation by an atomic layer depositedAl2O3 film was investigated.A 32 nm thick Al2O3 layer was found to be able to eliminate the hysteresis.