Total Power Dissipation Research Articles

A novel tunable capacitively-copuled instrumentation amplifier with 14.4 nV/ [formula omitted] z) noise and 190.47 nW micro-power for ECG applications

This paper describes a low-power, low-noise capacitively-coupled instrumentation amplifier (CCIA) designed for capturing biopotential signals. The main advantage of proposed design are as (i) CCIA based on new IA has been proposed, (ii) the lower cutoff frequency has been improved by adding MOS based resistor, (iii) gm enhancement circuit is added in operational transconductance amplifier (OTA) based fully differential difference amplifier (FDDA)to improve gain and bandwidth. The DC electrode-offset voltage is reduced and the input impedance is increased by using feedback mechanism. Cadence EDA tool is used to analyze the findings of the proposed CCIA's in 0.18 μm, CMOS technology with a 1.8 V power supply. The proposed CCIA architecture has an adjustable mid-band gain from 52.55 to 61.11 dB for bias voltage ranges from 0.1 to 0.6 V, frequency range of 0.06 Hz–1.72 kHz, and a CMRR of 122 dB. The proposed CCIA has a total power dissipation of 190.47 nW and equivalent input referred noise (IRN) of 14.4 nV/sqrtHz at 0.01 Hz. It only occupies 0.01 mm2 of core area. To assess the robustness of suggested design, PVT analysis, post layout simulation and a comparison with previously published works demonstrates the competence of the design.

Thermal-Hydraulic Characterization of a Thermosyphon Cooling System for Highly Compact Edge Microdatacenter

Abstract In the European project BRAINE, an extremely efficient passive thermosyphon cooling system was developed for a novel type of Edge MicroDataCenter (EMDC) with high heat fluxes to dissipate on individual computer cards and high heat dissipation rate per unit volume in the dense array of these cards. The primary objective was the cooling of 11 nodes (which include CPUs, FGPAs, GPUs and storage) considering one heat sink evaporator per node. The present study shows the experimental results obtained with the new environmentally friendly refrigerants R1233zd(E) and R1234ze(E) as well as a validation of the solver used to design the thermosyphon for a first demo EMDC with 4 slots (i.e 4 nodes). The maximal total dissipated power was 950 W and performance ratios of heat dissipation-to-cooling fan power up to 98-to-1 were obtained. The solver validation was performed by comparing pressure drop of the different components as well as the maximum temperature of the heaters mimicking CPUs for 232 simulated datapoints and proved extremely good accuracy without any scaling or empirical factors: 99%, 78%, 53% and 95% of the datapoints for the evaporator, riser, condenser and total pressure drop, respectively, were within 30% of the experimental results, which is accuracy comparable to the best two-phase pressure drop correlations in the literature, so a very good validation result. For the temperature validation, 97% of the datapoints were within 5°C of the experimental measurements, highlighting the robustness of the solver.

Monolithic integrated superconducting nanowire digital encoder

Superconducting digital circuits are promising technologies that can overcome bottlenecks in both classical and quantum computation due to their ultra-high operation speed and extremely low power dissipation. Superconducting nanowire cryotrons (nTrons) are emerging as one type of superconductor switching devices, offering advantages complementary to conventional Josephson junctions. Achieving monolithic integration of a reasonable number of nTrons into a functional digital circuit is a crucial step to extend its application. In this study, we constructed a monolithic integrated nTron-based binary encoder, which includes input fanout circuits, on-chip biasing, combinational logic routing and multi-gate nTrons. This represents a monolithic nTron digital circuit comprising 137 nTron gates, 424 resistors, 274 inductors, and 164 vias developed using a two-superconducting-layer fabrication process. The performance of this monolithic nTron encoder surpasses that of our previously demonstrated circuit with discrete nTron components. The maximum bias margin is 28% for the fanout circuit and 60% for the multi-gate nTron when using a signal generator, while the minimum timing jitter is 40 ps. The total power dissipation mainly from biasing resistors is 19.6 μW, making it more power efficient than RSFQ encoders. The encoder is then packaged and connected with a superconducting nanowire single-photon detector array for demonstrating its function of addressing pixel locations. Compared to the conventional readout, the nTron encoder shows a minimum readout error rate lower than 10−4 and reduces the readout RF lines from 15 to 4. The design and fabrication technologies could enrich integrated nTron digital circuits beyond current limits and promote their applications in classical and quantum systems.

Vehicle Surroundings Perception Using Micro‐electromechanical Systems Inertial Sensors

Sensors enable vehicles to perceive their surroundings even while parked. Camera‐based systems for vehicle surroundings perception are already available as of today. However, camera‐based systems result in excessive power consumption and data collection. In this article, a study on always‐on surroundings perception of parked vehicles is done using micro‐electromechanical systems (MEMS) inertial sensors as an alternative to camera‐based systems. The measurements of the MEMS inertial sensors are used to detect and classify 17 different types of events. These events include accidents, vandalism, rain, as well as normal use. A convolutional neural network (CNN) is used to classify the events. The data used to train the CNN is recorded using a test vehicle in a laboratory setting and on a test track. The CNN is quantized for deployment on a CNN hardware accelerator which is packaged with the sensor as a system‐in‐package (SiP). The novel sensor system achieves a classification accuracy of 88% at a total system power dissipation of 27 μW.

The Design of Low Power Op-amp for Biomedical Application

This work presents a low-power operational amplifier (op-amp) circuit design which optimized and tailored specifically for biomedical circuit application in low power environment. The proposed op-amp design incorporates the folded cascode differential amplifier technique with a low voltage supply 1.2 V, utilizing current biasing, current mirrors, and adopted low-power circuit topologies. AC and DC analysis are carried out to analyse the performance of the proposed design. Extensive simulations executed using industrial standard EDA tool have validated the circuit design, and demonstrated a gain of 70.94 dB, UGBW of 4.90 MHz, GM of 52.70 dB, PM of 82.02 degrees, PSRR of 82.77 dB, CMRR of 100.78 dB, and total power dissipation of only 28.07 mW. Low power consumption is essential for biomedical circuit applications, and the result shows a significant power reduction without compromising other performance parameters. The proposed op-amp circuit design is suitable to be implemented in low-power and high-performance biomedical devices.

Optimally Matched 189-232 GHz 6.8 dBm Output Power CMOS Frequency Doubler

This paper presents the design and measurements of a 215-252 GHz 40 nm bulk CMOS frequency doubler with a 6.8 dBm deliverable peak output power and a conversion gain of 11.8 dB. The designed chip is composed of a 28.5 dB gain 6-stages 110 GHz power amplifier, an optimized push-push doubler biased in class-C configuration, and an output impedance matching network. A numerical method had been applied here for designing each implemented matching network achieving the optimum matching while maintaining the minimum insertion loss as well. The presented design shows the highest output power among the other sub-THz-designed CMOS counterparts. The design occupies an area of 0.795 mm2 and shows a total DC power dissipation of 262 mW and DC-RF efficiency of 1.87%.

Dynamics of high-power coupled nonlinear oscillator arrays for electronic beam steering technique: case of the triode based van der Pol oscillator

This paper presents the dynamics of coupled nonlinear oscillator arrays (CNOAs) as phase shifter for electronic beam steering technique. The proposed phase shifter uses oscillators of van der Pol type with a fifth-order nonlinear resistance and is built on the two architectures based injection-locked oscillator array (ILOAs) and coupled oscillator arrays (COAs). The dynamics equations of the phase shifter are proposed in the frequency and time domain. With the help of mathematical tools such as bifurcation diagrams, maximum Lyapunov exponent and Hilbert transform, important cartography of different oscillating states is deduced over large range of system parameters. Different behavior of the CNOAs including chaos, 2D-torus, multistability, locked and unlocked states are depicted. The phase shift between output voltages of each pair of coupled oscillators is presented for both architectures. A detailed analysis of locked states shows that the required phase shift is synthesized by slightly varying the frequency of the injected signal, or simply by detuning the free-running frequencies of the edge oscillators in equal but opposite directions. The proposed circuit of the phased shifter is built using the original van der Pol oscillator based on a vacuum triode. The maximal phase shift reaches 63° and 75° respectively for ILOAs and COAs. With the presence of triode in the circuit, the output voltage of each oscillating element in the array reaches 100V around 60KHz and is boosted by increasing the value of the triode bias potential to more than 420V. This, therefore, increases the total power dissipation of a single oscillator in the array to more than 47dB ( 50.12W ). This circuit is a candidate for high-power electronics beam steering at ultrasonic frequency.

Design and Assessment of Hybrid MTJ/CMOS Circuits for In-Memory-Computation

Hybrid magnetic tunnel junction/complementary metal oxide semiconductor (MTJ/CMOS) circuits based on in-memory-computation (IMC) architecture is considered as the next-generation candidate for the digital integrated circuits. However, the energy consumption during the MTJ write process is a matter of concern in these hybrid circuits. In this regard, we have developed a novel write circuit for the contemporary three-terminal perpendicular-MTJs that works on the voltage-gated spin orbit torque (VG+SOT) switching mechanism to store the information in hybrid circuits for IMC architecture. Investigation of the novel write circuit reveals a remarkable reduction in the total energy consumption (and energy delay product) of 92.59% (95.81) and 92.28% (42.03%) than the conventional spin transfer torque (STT) and spin-Hall effect assisted STT (SHE+STT) write circuits, respectively. Further, we have developed all the hybrid logic gates followed by nonvolatile full adders (NV-FAs) using VG+SOT, STT, and SHE+STT MTJs. Simulation results show that with the VG+SOT NOR-OR, NAND-AND, XNOR-XOR, and NV-FA circuits, the reduction in the total power dissipation is 5.35% (4.27%), 5.62% (3.2%), 3.51% (2.02%), and 4.46% (2.93%) compared to STT (SHE+STT) MTJs respectively.

Evolution of the electrical characteristics of an atmospheric pressure dielectric barrier discharge system over one hour operation

In this work, long-time operation of a dielectric barrier discharge (DBD) characterized by a single thin dielectric was investigated. The discharge was operated under nitrogen at atmospheric pressure in a typical filamentary regime. Electrical measurements were performed, i.e. applied voltage, current and charge were retrieved. The Lissajous figure method combined with an equivalent circuit of the DBD was used to calculate the dissipated power, estimate the gas gap voltage , evaluate the deposited charges as well as the capacitances of the discharge cell. The results over a one-hour operation indicated that the total dissipated power remained constant, but a decrease of the gas gap voltage with an increase of the charge deposited was also depicted. For the capacitances, both dielectric and cell capacitances variations were studied from the Lissajous figures. The dielectric capacitance showed a voltage dependency over half a period of applied voltage.

Design and implementation of a Low power Adder Circuit Using LECTOR Technique

This work implements a 1-bit FA circuit with the CMOS logic with XOR-XNOR combinations. For sum and carry, pass transistors are used to generate the output by combining with XOR, XNOR and CMOS design, and the optimised full adder is implemented with the help of LECTOR technique to control the leakage power. As scaling of CMOS technology has shown improvement in the speed but the leakage power are left to act as major effect. low power VLSI is a new discipline in which high power consumption is becoming an important criteria. But when refers to battery life, high power dissipation is not recommended for device applications. It affects performance, raises cooling expenses, and shortens battery capacity. The switching, dynamic and leakage power changes the inputs significantly. There are several typical reduction strategies available to lower the energy of circuits. By implementing the reduced FA with the leakage power control technique the number of transistors reduced than the normal full adder. The proposed design has static and total power of 5.08nw and 8.33uw for XNOR and for XOR of 12.36nw and 8.56uw. A FA is designed using these technique the obtained results for static and total power are 12.38uw 8.58uw. For the above circuits, a comparison of various static and total power dissipations is conducted. CADENCE-VIRTUOSO is used to simulate circuits using 90nm technology with a 1.2V power supply.

Area & power modeling for different tree topologies of parallel prefix adders

Parallel prefix adder (PPA) being an indispensable component of processors needs prompt estimation of design metrics at the initial stage of design cycle. However, the available commercial tools take significant amount of time for the estimation process. The prior availability of area and power models can greatly reduce time-to-market. Symmetrical construction and quick computational ability of PPAs make them competent candidates for adder circuits in complex applications. This paper proposes area and power models for Field Programmable Gate Arrays (FPGA) implementation of classic PPAs, targeted to Xilinx Zynq-7000 family. The available literature barely presents parameters estimation and their analysis for PPAs. Therefore, modeling proposed in this paper is a novel work. PPA structures are simulated, synthesized and implemented using commercial tool i.e. VIVADO IDE. Models have been developed using curve fitting and validated against commercial tool. Results show an average estimation error ranging from 0.37% to 1.34% in case of area modeling and 0.23% to 0.59% in case of power modeling which are comparable with state of the art.

A Low-power Level-Crossing ADC for Biosignal Acquisition

A large number of redundant signals will be generated when the traditional Nyquist sampling method is used to acquire a biological signal, leading to a system’s energy loss. A new level-crossing analog-to-digital converter (LC-ADC) with non-uniform sampling and fixed window structure is presented, with fewer data and low power consumption features. The circuit uses a 6-bit capacitive DAC to quantize the input signal, avoiding the error accumulation of the 1-bit capacitive DAC structure, and a nanoamp CMOS current bias circuit to provide a very low quiescent current for the comparator, further reducing power consumption. The structure was verified in a 0.18μm CMOS technology. The results indicate that the total power dissipation is 0.26uw@500Hz, the signal-to-noise distortion ratio (SNDR) is 59dB@500Hz, and ENOB reached 9.51bit, which is suitable for the acquisition of low-frequency biological signals.

Design and Optimization of 4-Bit Array Multiplier with Adiabatic Logic Using 65 nm CMOS Technologies

ABSTRACT This paper proposes a 4-bit array multiplier useful in the design of basically mixer circuit, which is highly involved in signal and image processing using an efficient low-power VLSI technique. The presented architecture is completely implemented adiabatic techniques in the Near Threshold Region, which optimize the product of propagation delay and power dissipation. Multiplier is the most frequently used element in many digital electronics applications. Depending on the applications, various types of multipliers emerge. With this technique, the total power dissipation, i.e. dynamic power dissipation as well as static power dissipation is less as compared to the conventional CMOS technique. The Near Threshold Adiabatic Logic (NTAL) technique is used with a single timevarying power supply which reduces the clock tree management and enhances the energy-saving capability. Simulation of the proposed design is done by Cadence virtuoso schematic editor with specter simulator on TSMC 65 nm technology node to verify the optimized result. Also comparing our result to conventional CMOS techniques with all the same design parameters, the result shows that power dissipation improvement of approximately 66.6%, 14.4%, and 64.6% with respect to varying frequency, supply voltage, and load capacitance with other parameters keep constant such as if the frequency is varying than capacitance load value is C load = 10 pF and V DD(max) = 1.2 V, similarly if the supply voltage is varying than capacitance load value is C load = 10 pF and frequency F = 4 GHz and if load capacitance is varying than frequency F = 4 GHz and supply voltage V DD(max) = 1.2 V.

A Front-End CMOS Interface Circuit With High Voltage Charge Pump and Oscillator for Capacitive Micromachined Ultrasonic Transducers

Label-free biosensors, combined with miniaturized micro-electromechanical sensory platforms, offer an attractive solution for real-time and facile monitoring of biomolecules due to their high sensitivity and selectivity without the need for specifically labeling. Resonators have been acknowledged as an efficient technology for measuring biomolecular binding events including those involving nucleic acid and antibody. Among these, capacitive micromachined ultrasonic transducers (CMUTs) have emerged as a promising candidate for biosensing. However, their usage is often limited by the requirement for high voltage supply and continuous frequency tracking, which can result in significant parasitic effects and measurement errors. In this paper, we present a novel front-end interface circuit for a CMUTs-based biosensor. The circuit, fabricated using TSMC 0.18-μX;Jm Bipolar-CMOS-DMOS (BCD) technology, incorporates an on-chip high voltage charge pump and feedback frequency monitoring. The CMUTs array features 20×20 circular cells, fabricated using a low-temperature direct bonding technology, with an experimental parallel-resonant frequency of 1.724 MHz and a high quality factor of up to 40.9. To fit the measured electrical characteristics, a five-element equivalent lumped element model is proposed. The high voltage charge pump provides an output voltage of 20 V, while the feedback oscillator has a ms-level start-up time and a total power dissipation of 3.8 mW. The proposed front-end interface is designed to function as a stand-alone chip for CMUTs-based resonant biodetection.

Hardware architecture design for complementary ensemble empirical mode decomposition algorithm

In this paper, we have presented a field-programmable gate array (FPGA) as well as an application-specific integrated circuit (ASIC) based design for the complementary ensemble empirical mode decomposition (CEEMD) algorithm. CEEMD is an adaptive signal analysis method that decomposes an input signal into many signals, each of which is termed an intrinsic mode function (IMF). In this work, the CEEMD architecture is developed in the form of Verilog-HDL code. The ASIC is designed by using a 180 nm technology library. Our proposed ASIC can be operated at a clock rate of 58.82 MHz, and the total power dissipation of the ASIC is 76.20 mW. The core area of the CEEMD ASIC is 1.53 mm2. The FPGA-based design of CEEMD can work with a clock rate of 50 MHz, and Virtex-7 FPGA is used for the implementation purpose. The proposed parallel architecture of CEEMD extensively reduces the computational time of the design by employing parallel processing. FPGA and the ASIC-based design of CEEMD have very less computation time and can be used for real-time applications.

D-Band × 8 Frequency Multiplier Using Complementary Differential Frequency Doubler

A D-band <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times 8$ </tex-math></inline-formula> frequency multiplier is presented in this letter. The <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times 8$ </tex-math></inline-formula> frequency multiplier consists of two stages of the newly proposed common load complementary push-push doublers (CL-CPPDs) and one stage of NMOS push-push doubler. The proposed CL-CPPD uses a single load to generate a balanced output with high harmonic rejection (HR) and can be easily cascaded using transformers for a high multiplication ratio with low dc power consumption. The chip is fabricated by using a 40-nm CMOS technology, and it achieves a maximum output power of −2.48 dBm with an input power of 0 dBm in the frequency range of 131.2–144.8 GHz. All HRs are over 34 dBc in the frequency range of 131.2–144.8 GHz. The total dc power dissipation is 41.4 mW when supplied from a single voltage of 0.9 V and occupies 0.37 mm2 of the chip area.

A Low Spur 5.9-GHz CMOS Frequency Synthesizer with Loop Sampling Filter for C-V2X Applications

In this paper, a very low spur 5.9-GHz integer-N frequency synthesizer designed for a Cellular Vehicle-to-Everything (C-V2X) receiver is presented. The PLL is referenced to a 10-MHz crystal oscillator and the design is implemented in a 65-nm CMOS process. The output of the synthesizer has differential quadrature topology and provides the local oscillator signal to a downconverter mixer of C-V2X receiver. Post-layout simulations show that the reference spurs are better than −88[Formula: see text]dBc through loop sampling technique which was implemented in a 11.8-GHz VCO design for the first time to the best of our knowledge. The best spur level without the loop sampling technique applied is limited to −55[Formula: see text]dBc. Using the loop sampling technique provides a spur reduction of 33[Formula: see text]dB which is a significant improvement at this frequency. Based on post-layout simulations, the design has a phase noise of −97/−99/−114[Formula: see text]dBc for 10[Formula: see text]kHz/100[Formula: see text]kHz/1[Formula: see text]MHz frequency offsets, respectively, which presents competitive numbers with the designs in the literature. The design has 1.2-V nominal supply voltage for the analog and digital blocks. The total power dissipation of the synthesizer core is 6[Formula: see text]mW from a 1.2-V supply while the output buffers driving a 100-fF load consumes 18[Formula: see text]mW.

Novel tunable current feedback instrumentation amplifier based on BBFC OP-AMP for biomedical applications with low power and high CMRR

The paper presents a novel low power, low noise and high CMRR current feedback instrumentation amplifier (CFIA) design for biomedical signal acquisition i.e. EEG/ECG applications is presented. The proposed instrumentation amplifier performance is evaluated using 0.18μm, CMOS technology with 1.8 V supply and results are obtained in Cadence EDA tool. The proposed CFIA is implemented using a dual output bandwidth boosted folded cascode operational amplifier (BBFC OP-AMP) active block. In this paper the proposed CFIA performance parameters has been considered for optimization to get better results by using the idea of signal to noise ratio (SNR) with Taguchi design of experiments (Taguchi DoE) and analysis of variance (ANOVA) to estimate the most important independent variable which control the performance of the design. The bias voltage, channel length and width of input MOS transistors have been selected to optimize the proposed circuit performance. The proposed CFIA structure have 50.33 to 69.67 dB tunable differential gain, common mode rejection ratio (CMRR) of 143.19 dB, tunable bandwidth of 148.24 kHz to 1.31 MHz, dynamic range (DR) of 74.31 dB and 297.73 dB of figure of merit (FoM). The CFIA shows an equivalent input referred noise (IRN) of 0.586 μV at 0.1 Hz to 148.24 kHz frequency range, with total power dissipation of 102.73 μW and occupies 8194μm2 of core area. The simulation results of the proposed CFIA are close to the predicted solution obtained from ANOVA. The PVT analysis and post layout simulation has been performed to check the robustness of the proposed design. The proposed design has been compared with the other existing literature which shows the competence of the design.

Design of an Efficient CNN-based Cough Detection System on Lightweight FPGA.

Precisely and automatically detecting the cough sound is of vital clinical importance. Nevertheless, due to privacy protection considerations, transmitting the raw audio data to the cloud is not permitted, and therefore there is a great demand for an efficient, accurate, and low-cost solution at the edge device. To address this challenge, we propose a semi-custom software-hardware co-design methodology to help build the cough detection system. Specifically, we first design a scalable and compact convolutional neural network (CNN) structure that generates many network instances. Second, we develop a dedicated hardware accelerator to perform the inference computation efficiently, and then we find the optimal network instance by applying network design space exploration. Finally, we compile the optimal network and let it run on the hardware accelerator. The experimental results demonstrate that our model achieves 88.8% classification accuracy, 91.2% sensitivity, 86.5% specificity, and 86.5% precision, while the computation complexity is only 1.09M multiply-accumulation (MAC). Additionally, when implemented on a lightweight field programmable gate array (FPGA), the complete cough detection system only occupies 7.9K lookup tables (LUTs), 12.9K flip-flops (FFs), and 41 digital signal processing (DSP) slices, providing 8.3 GOP/s actual inference throughput and total power dissipation of 0.93 W. This framework meets the needs of partial application and can be easily extended or integrated into other healthcare applications.

Improved Design for the High Gain Wideband Matrix Amplifiers Using Differential Cells and Microwave CMOS Technology

The Matrix Amplifier is a structure designed to increase the gain of the wideband distributed amplifiers. A matrix amplifier is used to improve the pass-band gain while preserving the dispersed design-wide characteristics to use the multiplicative gain mechanism. In this paper, the matrix distributed amplifier methodology is developed using differential cells instead of active amplifier cells to improve the wideband characteristics. Shunt capacitances are connected in the centerline to absorb the peaking impact at a cut-off frequency and reduce gain ripples. As an application of the ideas and concepts of matrix amplifiers, a modified step-by-step design of rows 4 and column 2 matrix amplifier is undertaken using a Quasi Differential amplifier. A Matrix differential amplifier using a shifted-second-tier structure technique is then built and tested in 0.18 µm Complementary Metal Oxide Semiconductors technology. The advantages gained from the proposed design are high gain, high bandwidth, low noise, and no need for balun circuits. The design and simulation results were achieved using ADS. The significant results show a high gain of 40 dB and a 33 GHz bandwidth. The noise figure is also 3.583, with S11, S22, and S12 being -10 dB, -10dB, and -40dB, respectively; the output power at 1-dB gain compression point is evaluated (P1dB) of +6.4 dBm, and the total DC power dissipation is 266mW. The cadence tools produced the layout design and specifications, although the chip size was 1.1mm2.