Total Power Dissipation Research Articles

A 103 dB DR Fourth-Order Delta-Sigma Modulator for Sensor Applications

This paper describes a fourth-order cascade-of-integrators with feedforward (CIFF) single-bit discrete-time (DT) switched-capacitor (SC) delta-sigma modulator (DSM) for high-resolution applications. This DSM is suitable for high-resolution applications at low frequency using a high-order modulator structure. The proposed operational transconductance amplifier (OTA), used a feedforward amplifier scheme that provided a high-power efficiency, a wider bandwidth, and a higher DC gain compared to recent designs. A chopper-stabilization technique was applied to the first integrator to remove the 1/f noise from the transistor, which is inversely proportional to the frequency. The designed DSM was implemented using 0.35 µm complementary metal oxide semiconductor (CMOS) technology. The oversampling ratio (OSR) was 128, and the sampling frequency was 128 kHz. At a 500 Hz bandwidth, the signal-to-noise ratio (SNR) was 100.3 dB, the signal-to-noise distortion ratio (SNDR) was 98.5 dB, and the dynamic range (DR) was 103 dB. The measured total power dissipation was 99 µW from a 3.3 V supply voltage.

A New Configurable Wireless Sensor System for Biomedical Applications with ISO 18000-3 Interface in 0.35 µm CMOS.

This article presents a new configurable wireless sensor system. The system is used to perform amperometric measurements and send the measurement data to a handheld reader using a wireless transponder interface. The two-chip sensor system was implemented in a 0.35 μm CMOS technology. The system consists of an integrated nano-potentiostat that performs the actual measurements and an ISO 18000-3 compliant frontend that enables wireless telemetric data transmission and powering of the entire sensor system. The system was manufactured in combination with a chronoamperometric glucose sensor which allows the measurement of the glucose content in tear fluid and thus a non-invasive determination of the blood sugar level. For a range of sensor currents from 0.1 μA to 10 μA, the potentiostat achieved an accuracy of better than 5 % with a total power dissipation of less than 600 μW. With the realized antenna geometry a wireless communication distance of more than 7 cm has been achieved.

Design of a low-power 12.5Gb/s 1:10 demultiplexer in 0.18μm CMOS*

A low-power 12.5Gb/s 1:10 Demultiplexer (DEMUX) without inductors is designed in 0.18μm CMOS (Complementary metal oxide semiconductor) process. The 1:10 DEMUX includes a high-speed 1:2 DEMUX, two serial low-speed 1:5 DEMUX, a 5 frequency divider and so on. The latch of the high-speed 1:2 DEMUX adopts the CML (Current Mode Logic) structure. The rest of the triggers all use E-TSPC(Extended True Single Phase Clock)structure. In the design of the 5 frequency divider, the logic gate circuit is embedded in flip-flop to improve the work frequency. The post simulated result shows that when the data rate of the input pseudorandom is 12.5Gb/s and the clock frequency is 6.25GHz at a supply voltage of 1.8V, this1:10 DEMUX can work well and the eye diagram of output data is clear. The output swing is 400mV on an external 50 Ohm load and the total power dissipation is 200mW. The die size is 0.64×0.57mm2.

Alternative statements of the Rayleigh monotonicity law for linear time-invariant resistor networks driven by only voltages or only currents

Networks of linear time-invariant (LTI) resistors are a classical topic with many applications, used to model a variety of flow phenomena. In this short communication, we provide conceptually simple proofs of the following intuitively appealing bounds, which also imply the classical Rayleigh monotonicity law (RML): (i) For an LTI resistor network, driven by some node voltages, when a set of resistors is removed the total power dissipation is reduced by at least an amount that was consumed in the removed resistors. (ii) The complementary or dual result for such a network, but when current driven, is that shorting some resistors decreases the total power dissipation by at least as much as used to occur in these resistors before shorting. In fact, ideal diodes can be allowed as network branches and the same results hold. The short derivations assume that Dirichlet's and Thomson's minimum principles are known. With the expanding applications of a linear network theory, we hope that these variants of the monotonicity theorem will prove pedagogically useful.

Design and test of driver and readout ASICs for scientific CCD detectors

In order to implement the driver and readout functions for a variety of scientific CCD detectors, especially for the prime-focus optical camera of the 2.5-meter Wide Field Survey Telescope (WFST), including decreasing the size of electronics and reducing the total power dissipation, two Application-specified Integrated Circuits (ASIC) were designed. One is used for CCD drivers and named as Bias-Clock-Driver ASIC (BCDA), which provides multi-channel clocks and bias voltages, the other is for CCD video signal processing and called CCD-Video-Readout ASIC (CVRA). The first prototype of BCDA and CVRA has been finished with the Global Foundries 180 nm BCDlite technology. In this paper, the design and layout of two ASICs, the design of testing system, the function and performance testing of two ASICs are introduced. The test results show that the high level range of clock is from 8 V to 16 V. The rise/fall time of parallel clock is several microseconds and the frequency is more than 100 kHz. The rise/fall time of serial clock is dozens of nanoseconds and the frequency is more than 1 MHz. The noise of the readout circuit is 9.2 e− when the readout speed is 100 kHz. The test results indicate that this design has achieved the goal of functional verification. And performance will be improved in subsequent design, especially in readout noise.

Proposed Design of 1 KB Memory Array Structure for Cache Memories

Technology scaling facilitates to meet ever increasing demands for a portable and battery operated systems, at the same time causes diminution of length of the channel, gate oxide layer and threshold voltage which increases the leakage or static power at a standby mode. Static or leakage power is the dominating factor of total power dissipation in deep nanometer technologies below 90 nm. In memory design, parameters such as power, delay and stability of the memory are considered for which affects the performance of the memory. Static random access memory (SRAM) is a type of RAM, which does not need to be refreshed periodically and data is not written permanently in it. This manuscript dedicates in designing 256 × 4 memory array structure using imminent SRAM cell and sense amplifier for usage as cache memories in most modern computer systems. The other sustaining devices in executing this array structure are row decoder, column decoder and control unit. Design metrics such as static power, dynamic power, delay, power delay product, energy, energy delay product, rise time, fall time and slew rate are taken into account. All the circuits were designed using SYNOPSYS EDA tool and simulated in 30 nm technology. Simulation results shows that array structure designed using proposed SRAM cell and sense amplifier provides better performance than existing array structure.

Design of Novel SRAM Cell Using Hybrid VLSI Techniques for Low Leakage and High Speed in Embedded Memories

Static or leakage power is the dominating component of total power dissipation in deep nanometer technologies below 90 nm, which has resulted in increase from 18% at 130 nm to 54% at 65 nm technology due to continued device and voltage scaling. Static random access memory (SRAM) is a type of RAM in which data is not written permanently and it does not need to be refreshed periodically. Different techniques have been applied to SRAM cell to reduce leakage power without affecting its performance. A novel 10T SRAM architecture is proposed in this paper which operates in three modes (active, park, standby or hold). The main objective of the proposed architecture is to provide better stability and reduced delay in active mode, reduced leakage current in standby mode and retaining the logic state in park mode. Design metrics such as static and dynamic power, delay, power delay product, energy, energy delay product, rise and fall time, slew rate and static noise margin are taken into account. All the circuits were designed using SYNOPSYS EDA tool and simulated in 30 nm technology. Simulation results shows that the proposed SRAM is much better than conventional and other SRAM cells designed using hybrid techniques.

Virtual texturing of lightweight engine crankshaft bearings

This paper aims to numerically study the effects of surface texturing on reducing the power loss and lift increasing in lightweight crankshaft bearings. A computer program was developed to study the behavior of a dynamically loaded engine crankshaft bearing taking into account roughness effects and surface texturing using dimples. We compare results using the Patir and Cheng modified Reynolds equation and the so-called $$p-\theta $$ model proposed by Elrod and Adams. In addition, the JFO mass-conserving model is considered to deal with cavitation. The finite difference method is used to approximate the Patir–Cheng Reynolds equation. Simulations were performed for the main bearing of the lightweight crankshaft, considering different surface texture designs in terms of location, depth and radius of dimples. Some texture designs lower the hydrodynamic fluid pressure peaks by 4.8%, consequently providing additional lift. Lastly, a comparison between the lightweight and regular crankshaft bearings is also considered. The total dissipated power was reduced by 3.6% for the textured lightweight crankshaft bearing.

The concept of high dielectric material for the treatment of liver cancer through microwave heating

Hyperthermia is potentially an effective method for the treatment of cancer tumours. In the present manuscript, improvement in the treatment of liver cancer through electromagnetic heating is studied using high dielectric material through mathematical modelling in COMSOL Multiphysics. It is observed from the result that without increasing the power input, intensity of the temperature can be increased by changing the dielectric constant. Treatment time in ablation of the liver tumour can also be reduced. Results are obtained for total power dissipation density, heat flux, temperature distribution and fraction of necrosis tissue.

Voltage Differencing Buffered Amplifier based Voltage Mode Four Quadrant Analog Multiplier and its Applications

In this paper a voltage mode four quadrant analog multiplier (FQAM) using voltage differencing buffered amplifier (VDBA) based on quarter square algebraic identity is presented. In the proposed FQAM the passive resistor can be implemented using MOSFETs operating in saturationregion thereby making it suitable for integration. The effect of non idealities of VDBA has also been analyzed in this paper. Theoretical propositions are verified through SPICE simulations at 0.18μm CMOS technology node and the simulation results are found in close agreement with theoretical values. The supply voltage is taken as ± 1V and the value of the bias current is set to 40µA.The simulated total harmonic distortion (THD) is observed to be under 3% and the total power dissipation is found as 627µW. The workability of the proposed FQAM is also tested through two applications, namely, an amplitude modulator and a rectifier. The simulated results corroborate the theoretical propositions.

PERFORMANCE ANALYSIS OF FULL ADDERS IN CIC DECIMATION FILTER

This article presents analysis of various full adder architecture on Cascaded Integrator-Comb (CIC) filter of delta-sigma ADC. The structure of CIC filter consists of an integrator and a differentiator stage that is built from a cascaded full adder and delay element. Since each of the element within CIC filter has its own low-power architecture, full adder is one of the block that consumes huge amount of power compared to others. In this paper, four different type of full adder’s architecture is designed and simulated with CIC decimation filter. There are 28T conventional, pseudo-NMOS adder, 16T hybrid adder and modified 14T hybrid adder. The performance parameters such as delay, total power dissipation and power delay product (PDP) of CIC filter were compared. This analysis shows that 16T hybrid full adder CIC filter has reduced up to 38.15% of power consumption and 39.18% of power product delay compared to conventional adder. Hence, a complete 1-bit third order of 16T hybrid adder CIC filter is implemented with size area of 118.23µm × 22.38µm.
 Keywords: Delta-sigma ADC, Low-power, CIC decimation filter, Full adder

A design of ± 0.28 ppm temperature-compensated crystal oscillator in a 0.35 μm CMOS process

A high-performance temperature-compensated crystal oscillator (TCXO) is presented. This paper proposes a new temperature sensor with a Σ–Δ analog to digital converter, and a voltage-controlled crystal oscillator, respectively, using two sets of independent power supply. The presented TCXO is implemented in a 0.35 μm 2P3 M standard complementary metal-oxide semiconductor process at a power supply of 3.3 V, and the total power dissipation is 21 mW. Measurement results indicate that the designed TCXO achieves ± 16 ppm output frequency tuning range and 135, − 141 dBc/Hz phase noise at 1, 10 kHz frequency offset, respectively, by using a 40 MHz fundamental AT-cut crystal resonator. With the temperature compensation, the frequency deviation is within ± 0.28 ppm over − 40 °C to 85 °C.

Add-On Microchannels for Hotspot Thermal Management of Microelectronic Chips in Compact Applications

This paper demonstrates an experimental micro- channel solution to cool microelectronic chips with hotspots, using an integrated, yet nonintrusive technique. In microelectronics, approaches such as die thinning induce acute stress on cooling because it increases the hotspot phenomena and reduces chip bulk thickness that could be used for microchannels. In compact devices, heat must be removed using limited pumping power and cooling space. Microchannels etched in the backside of the chip, usually considered as an efficient cooling solution, are impracticable on highly thinned chips. This paper experimentally investigates the cooling performance of a noninvasive and hotspot aware microchannel die that is in direct fluidic contact with the backside of the microelectronic chip. It also proposes a confinement-wise metric. A thermal resistance of 2.8 °C/W is achieved at a heat flux of 812 W/cm2 per heat source, for a total dissipated power of 20 W and a maximum allowed temperature rise of 55 °C. Such performance is obtained with only 19.2 kPa of pressure drop and 9.4 ml/min of flow rate, corresponding to a hydraulic power of only 3 mW and a coefficient of performance of 6500. In addition, the complete chip stack, including the thinned chip, measures only $660~\mu \text{m}$ high. Therefore, backside cooling appears to be a promising compact and low consumption solution for compact electronic applications having confined hotspots.

A −40 dB EVM, 77 MHz Dual-Band Tunable Gain Sub-Sampling Receiver Front End in 65-nm CMOS

In this paper, the first dual-band sub-sampling receiver front end with sampling frequency optimization to meet the ultimate receiver error vector magnitude (EVM) of −40 dB over wide input power range of 19 dB is proposed. A systematic sub-sampling receiver chain EVM optimization with respect to major system-level impairments, such as noise folding, sampling frequency, IQ mismatches, phase noise of the sub-sampling clock, and unit capacitor value realizable at the decimation filter, is presented. The proposed dual-band sub-sampling receiver has a 26–41 dB continuously tunable gain for 2.4 GHz and 26–38.5 dB for the 5 GHz WLAN band. Continuously tunable gain ensures the ultimate receiver EVM performance over wider input power levels. In addition, the 5 GHz band is continuously tunable from 4.5 to 5.7 GHz. An active balun feedback low-noise amplifier followed by a sub-sampling down-conversion mixer is implemented to down-convert both WLAN bands to an intermediate frequency in the range from 445 to 538 MHz. Sub-sampling frequency optimization proposed in this paper down-converts both WLAN bands with the sampling frequency from 1.78 to 2.15 GHz to reach the target EVM. Additionally, a switched capacitor decimation filter running at 90 MHz is implemented to provide dual functionalities of down-conversion to baseband and band selection. A test-chip is implemented in a 1.2 V 65-nm CMOS technology. The proposed dual-band sub-sampling receiver occupies a total active area of 0.72 mm2 and has a total power dissipation of 55.6 mW. The overall receiver chain shows a noise figure of 11.5 dB at the highest gain and an IIP3 of −8 dBm at the lowest gain.

Power Scheduling With Active <inline-formula> <tex-math notation="LaTeX">$RC$ </tex-math> </inline-formula> Power Grids

Power gating is widely used in large chip design as a way to manage the total power dissipation and avoid overheating. It works by turning OFF the power supply to circuit blocks that are not required to operate in certain operational modes. Many authors have studied the scheduling of chip workload to manage total power and temperature. But power gating also has an impact on the supply voltage levels across the die, because voltage drop is generated in the grid depending on the combination of blocks that are ON. We consider the question of how to manage the chip workload so that supply voltage variations remain within specs. The worst case voltage drop is the result of two things: the power budgets that were allocated to the various circuit blocks during the design process and the combination of blocks that are turned ON in a given operational mode. In this paper, we propose a framework to manage this tradeoff between how many blocks are ON simultaneously and how big the power budgets of the individual blocks are, assuming resistive and capacitive (RC) elements in the power grid model. Subject to user guidance, we generate block-level circuit current constraints as well as an implicit binary decision diagram (BDD) that helps identify the safe working modes. If the blocks are designed to respect these constraints, then the BDD can be used during normal operation to check whether a candidate working mode is safe or not.

Radix-8 Design Alternatives of Fast Two Operands Interleaved Multiplication with Enhanced Architecture

Abstract In this paper, we proposed different comparable reconfigurable hardware implementations for the radix-8 fast two operands multiplier coprocessor using Karatsuba method and Booth recording method by employing carry save (CSA) and kogge stone adders (KSA) on Wallace tree organization. The proposed designs utilized ALTERA Cyclone IV FPGA family with target chip device EP4CGX–22CF19C7 along with simulation package. Also, the proposed designs were synthesized and benchmarked in terms of the maximum operational frequency, the total path delay, the total design area and the total thermal power dissipation. The experimental results revealed that the best multiplication architecture was belonging to Wallace Tree CSA based Radix-8 Booth multiplier (WCBM) which recorded: critical path delay of 14.103 ns, maximum operational frequency of 90.83 MHz, hardware design area (number of logic elements) of 14249 LEs, and total thermal power dissipation estimated as 217.56 mW. Consequently, WCBM method can be efficiently employed to enhance the speed of computation for many multiplication based applications such embedded system designs for public key cryptography.

Cost effective FPGA Implementation of Right-to-Left Modular Exponentiation with NAF-Representation

Modular exponentiation is an exponentiation performed over a modulus. It is useful in computer science, especially in the field of public-key cryptography. Most technological applications of modular arithmetic involve exponentials with very large numbers. In this paper, we propose a high radix reconfigurable implementation for the Right-to-Left Modular Exponentiation with NAF-Representation by exploiting the maximum possible parallelism of the internal operations. The proposed design targeted the ALTERA Cyclone IV FPGA (EP4CGX22CF19C7) along with Quartus II simulation package. The proposed design was evaluated in terms of the maximum operational frequency, the total path delay, the total design area and the total thermal power dissipation. The synthesized results revealed that the proposed high radix architecture implementation has recorded: critical path delay of 25.5 ns, maximum operational frequency of 44.59 MHz, hardware design area (number of logic elements) of 2556 LEs, and total thermal power dissipation estimated as 221.82 mW. Consequently, the proposed modular exponentiation architecture can be efficiently employed by many public key cryptographic mechanisms.

Performance Analysis of 128-bit Modular Inverse Based Extended Euclidean Using Altera FPGA Kit

Modular inverse is a division operation performed over a modulus and is considered as a fundamental operation for many public-key cryptosystems. Extended Euclidean Algorithm (EEA) is considered one of the most efficient algorithms to compute the modular multiplicative inverse of two coprime numbers. In this paper, we are reporting on the FPGA implementation of 128-bit modular inverse unit using Extended Euclidean Algorithm (EEA) algorithm with maximum possible parallelism of the internal operations. To verify the deposed implementation, we have synthesized our VHDL coding using ALTERA Cyclone IV FPGA with target device EP4CGX22CF19C7 using Quartus II simulation package. The experimental results showed that the proposed implementation recorded a critical path delay of 16.84 ns with maximum operational frequency of 72.7 MHz. Also, the area of the proposed design was estimated as the number of logic elements (LEs) utilized by the proposed unit which is reported as 7157 LEs. Finally, the power dissipation of the proposed using was estimated as the total FPGA thermal power dissipation and reported as 231.41 mW. Hence, the proposed modular inverse module can be efficiently embedded with many FPGA based cryptographic applications.

A Chopper Stabilized Current-Feedback Instrumentation Amplifier for EEG Acquisition Applications

A low-noise, low-power, chopper-stabilized, current-feedback instrumentation amplifier (CFIA) for bio-potential signal acquisition applications is presented. The proposed design includes an ac-coupled chopper-stabilized CFIA to reduce 1/f noise. It also has a switched-capacitor integrator to reduce the input offset and provide a high-pass filter. The proposed amplifier is designed using a Samsung 0.13-μm CMOS process. The CFIA shows an rms input referred noise voltage of 0.75 μV within a bandwidth of 0.01-100 Hz, a common-mode rejection ratio of 125 dB, and total power dissipation of 2.3 μW at a power supply voltage of 1 V.

A Chopper-Stabilized Amplifier With a Tunable Bandwidth for EEG Acquisition Applications

A chopper-stabilized amplifier for bio-potential signal acquisition applications is presented. The proposed design includes an AC-coupled chopper-stabilized amplifier to reduce the 1/f noise and a tunable MOS-capacitor and a tunable pseudo-resistor to control the bandwidth. It employs a positive feedback input impedance boosting loop (IBL) to increase the input impedance and common-mode rejection ratio (CMRR). The proposed amplifier is designed and fabricated using a Magnachip/SK Hynix $0.18~\mu \text{m}$ 1 poly-6 metal CMOS process and tested with a DC supply voltage of 1.5 V ( $V_{\mathrm {DD}}$ of 0.75 V and $V_{\mathrm {SS}}$ of −0.75 V). The proposed amplifier achieves a midband gain of 47.6 dB, a CMRR of 105.6 dB, and an input-referred noise power spectral density (PSD) of $120~\text{nV}/\surd\text{Hz}$ at 100 Hz with a total power dissipation of 855 nW. The noise-efficiency-factor (NEF) of the proposed amplifier is 2.91. The low-pass corner frequency can be tuned from 200 to 500 Hz. The chip area of the proposed amplifier is 0.065 mm2.