Total Dose Radiation Hardness Research Articles

Dependence of total dose response of bipolar linear microcircuits on applied dose rate

The effect of dose rate on the total dose radiation hardness of three commercial bipolar linear microcircuits is investigated. Total dose tests of linear bipolar microcircuits show larger degradation at 0.167 rad/s than at 90 rad/s even after the high dose rate test is followed by a room temperature plus a 100/spl deg/C anneal. No systematic correlation could be found for degradation at low dose rate versus high dose rate and anneal. Comparison of the low dose rate with the high dose rate anneal data indicates that MIL-STD-883, Method 1019.4 is not a worst-case test method when applied to bipolar microcircuits for low dose rate space applications. >

Radiation hardened high performance CMOS VLSI circuit designs

For space or nuclear plant applications, radiation tolerant high performance CMOS VLSI circuit designs, utilising scaled CMOS/SOS technology and scaled bulk CMOS technology, have been reviewed, placing strong emphasis on total dose radiation hardness. Based on radiation induced degradations for conventional CMOS circuits, such as inverters, ring oscillators and memory circuits, total dose radiation hardening technologies have been discussed. Low temperature process and thin oxide introductions are effective for radiation induced threshold voltage shift reduction. Total dose radiation induced field leakage is suppressed by introducing a thin field oxide between the source/drain diffusion layers and a thick field oxide in NMOS transistors, combined with the buried P+ diffusion layer at the P well edge, without sacrificing speed performance. In addition to device/process technologies for total dose radiation hardening, usefulness for NAND logics and static circuits in radiation tolerant CMOS VLSI designs, are shown. Furthermore, radiation tolerance superiority of clocked gate CMOS circuits to transfer gate CMOS circuits in SOS devices, are indicated. Latchup immunity and SEU immunity have also been discussed, for both SOS and bulk devices. Effectiveness of epitaxial substrate and wide transistor introductions for latchup and SEU prevention, is shown, respectively. CMOS/SOS radiation hardened VLSIs and bulk CMOS radiation hardened VLSIs which have been developed by utilising above mentioned technologies, are reported. The entire work described in this paper has made it possible to design radiation hardened high performance VLSI circuits for space or nuclear plant applications, utilising both CMOS/SOS technology and bulk CMOS technology.

Evaluation of 850 degrees C wet oxide as the gate dielectric in a 0.8- mu m CMOS process

The authors describe a detailed comparison of a 850 degrees C wet oxide and a 900 degrees C dry oxide as the MOS gate dielectric in a 0.8- mu m CMOS process. The device fabrication involves a GE 0.8- mu m CMOS process. Emphasis is given to poly-Si gate linewidth measurements which are crucial to the interpretation of the results. The comparison of thin oxide integrity, device characteristics, hot-electron reliability, and total-dose radiation hardness between the two oxides is discussed. Specifically, it is pointed out why the PMOS punchthrough voltage requirements mandate the use of a 850 degrees C wet oxide for the gate dielectric.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Total dose radiation hardness of diamond-based silicon-on-insulator structures

Total dose radiation hardness measurements were performed on silicon-on-insulator (SOI) test structures where the insulator is chemical vapor deposited (CVD) diamond. These measurements represent a first look at the fundamental radiation response of low-pressure CVD synthetic diamond materials for SOI applications. Silicon/diamond metal-insulator-semiconductor (MIS) capacitors were subjected to both cobalt-60 and 10 keV x-ray irradiation up to doses of 1×107 rad (SiO2) while under positive, negative, and zero bias conditions. The diamond insulators used in these devices were found to be free from extensive hole or electron trapping. This behavior is consistent with the high electron and hole mobility of the polycrystalline diamond insulator.

A radiation-hardened 10 K-gate CMOS gate array

A radiation-hardened 10013-gate complementary metal-oxide-semiconductor (CMOS) gate array with a 5-V supply voltage has been designed and fabricated utilizing Si-gate epi-CMOS technology with two-level metallization. The n-channel (NMOS) and p-channel (PMOS) gate lengths in basic cells are 2 mu m. A 100-krad(Si) total-dose radiation hardness has been realized by introducing a thin field oxide between the source and drain diffusion layers and a thick field oxide in NMOS transistors in both the basic cells and the I/O cells, as well as a buried p/sup +/ diffusion layer under a poly-Si layer at the p-well edge in the basic cells, without sacrificing speed and performance. The gate array can be used to realize various kinds of radiation-tolerant logic LSIs for space and nuclear plant applications. >

Total dose radiation hardness of MOS devices in hermetic ceramic packages

The total-dose radiation hardness of hardened MOS transistors is experimentally shown to be degraded by hydrogen gas commonly trapped in hermetic-ceramic-package cavities. This introduces another variable to be considered in the manufacture and hardness assurance of total-dose-hardened integrated circuits. The observation also extends the link between hydrogen and interface-state formation to the understanding of hydrogen's role in ionizing radiation effects. It is concluded from experiments in which hydrogen is diffused into irradiated oxides after Co-60 exposure that the diffusing hydrogen interacts with independently created radiation damage to form interface states. >

Total Dose Effects in the 54HC Family of Microcircuits

Motorola and National Semiconductor 54HC00 and 54HC74 microcircuits were evaluated using CO-60 to determine their total dose radiation hardness. The devices were found to be radiation soft failing parametrically between 5 and 10 K rads and functionaly between 20 and 40 K rads. The failures were bias dependent, relatively insensitive to dose rate, and only annealed moderately when left unbiased at room temperature.

Sem irradiation for hardness assurance screening and process definition

Low-energy electron irradiation of complementary metal-oxide semiconductor (CMOS) devices has been correlated to cobalt-60 gamma irradiation in terms of oxide space charges and interface states. <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup> This paper reports on the results obtained using the low-energy electron beam of a standard commercial scanning-electron-microscope (SEM) for in-process hardness assurance screening and as a tool for rapid evaluation of process variations designed to improve total-dose radiation hardness. The techniques for SEM testing are described, and the results of correlation studies of radiation effects produced by the SEM, gamma radiation (Co-60), and 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> -eV sources compared. The variance in total dose radiation hardness over a single wafer and from wafer to wafer has been investigated for the CMOS CD-4007 array and the results are reported.