Toggle Flip-flop Research Articles

The dependence of operating frequency of NbN Toggle Flip-flop on parameters of NbN Josephson junctions

We performed a comprehensive investigation of the relationship between the maximum operating frequency of the NbN superconducting frequency divider and the key parameters of the NbN Josephson junction (JJ). We designed a superconducting frequency divider that uses a single NbN JJ as a pulse generator, several NbN Josephson transmission lines, an NbN Toggle Flip-flop, and a load. By comparing the bias voltage V in of the pulse generator with the output voltage V out of the load, we determined if the circuit was working correctly and calculated the maximum operating frequency f max. Additionally, we employed JSICsim software for simulations to analyze the impact of key parameters of the NbN JJ, such as critical current density J c, gap voltage V g, characteristic voltage V c, quality factor Q, and specific capacitance C s, on f max. The simulation results demonstrate that f max increases with increasing J c and Q. Specifically when J c exceeds 300 kA cm−2 and Q surpasses 4, the superconducting frequency divider can achieve a f max of 1 THz. Furthermore, we successfully fabricated a superconducting frequency divider using a 10 kA cm−2 process and tested a f max of 260 GHz, with a deviation of approximately 6% from the simulation results.

NbN-based tunnel-type π-junctions for low-power half-flux-quantum circuits

We have developed half-flux-quantum (HFQ) circuits using all-π-junctions formed from an NbN/AlN/PdNi/NbN (SIFS) structure. The circuits were fabricated using a novel process that incorporated a ground plane on top of the chip, enabling the epitaxial growth of NbN-based junctions from the substrate. The π-state of the junctions was demonstrated through a HFQ shift. Notably, these π-junctions exhibited self-overdamped current-voltage characteristics, enabling them to function as switching components without the need for shunt resistors. The elimination of shunt resistors and the high sheet inductance of NbN are expected to enhance the density of HFQ circuits. To evaluate the performance and power consumption of the all-π-junctions HFQ circuits, we designed and fabricated an HFQ toggle flip-flop (HFQ-TFF) circuit utilizing π-π-π SQUIDs as the fundamental components. Our findings reveal that the NbN-based HFQ-TFF circuit correctly operates as a frequency divider while consuming only around 30% of the power compared to single-flux-quantum TFF (SFQ-TFF) circuits. These results suggest that the HFQ circuit using SIFS-π-junctions has promising potential for integrated circuits requiring low-power consumption at cryogenic temperatures, such as qubit control.

CMOS Clock-Gated Synchronous Up/Down Counter With High-Speed Local Clock Generation and Compact Toggle Flip-Flop

CMOS Clock-Gated Synchronous Up/Down Counter With High-Speed Local Clock Generation and Compact Toggle Flip-Flop

Energy efficient half-flux-quantum circuit aiming at milli-kelvin stage operation

Half-flux-quantum (HFQ) circuits are based on 0–π superconducting quantum interference devices (SQUIDs) and is one of the energy-efficient superconductor digital circuits. The bit energy is determined by the critical current I cn of 0–π SQUID, which can be easily tuned with the loop inductance and junction critical current. In this work, an alternative π–π–π SQUID is adopted to demonstrate HFQ circuits to simplify the fabrication process and enhance circuit energy efficiency. The properties of superconductor/ferromagnet/insulator/superconductor Josephson junctions (π-JJs) are measured with temperature dependence from 4.2 K down to 10 mK. HFQ toggle flip-flops (TFFs) are successfully demonstrated at frequencies of up to 6.7 GHz and 44.5 GHz at temperatures of 4.2 K and 10 mK, respectively. Comparing the HFQ TFF with its rapid single-flux quantum counterpart under the same fabrication process, it is anticipated that the HFQ TFF will exhibit approximately 70% reduction in both static and dynamic energy dissipation. This research establishes the foundation for developing cryogenic interface control and readout circuits for large-scale quantum computing in the future.

Novel ultra-energy-efficient reversible designs of sequential logic quantum-dot cellular automata flip-flop circuits

Quantum-dot cellular automata (QCA) is a technological approach to implement digital circuits with exceptionally high integration density, high switching frequency, and low energy dissipation. QCA circuits are a potential solution to the energy dissipation issues created by shrinking microprocessors with ultra-high integration densities. Current QCA circuit designs are irreversible, yet reversible circuits are known to increase energy efficiency. Thus, the development of reversible QCA circuits will further reduce energy dissipation. This paper presents novel reversible and irreversible sequential QCA set/reset (SR), data (D), Jack Kilby (JK), and toggle (T) flip-flop designs based on the majority gate that utilizes the universal, standard, and efficient (USE) clocking scheme, which allows the implementation of feedback paths and easy routing for sequential QCA-based circuits. The simulation results confirm that the proposed reversible QCA USE sequential flip-flop circuits exhibit energy dissipation less than the Landauer energy limit. Irreversible QCA USE flip-flop designs, although having higher energy dissipation, sometimes have floorplan areas and delay times less than those of reversible designs; therefore, they are also explored. The trade-offs between the energy dissipation versus the area cost and delay time for the reversible and irreversible QCA circuits are examined comprehensively.

Hardware Random Number Generator Using Josephson Oscillation and SFQ Logic Circuits

A hardware random number generator using Josephson oscillation and a few single flux quantum (SFQ) logic gates is presented. The logic circuit of the random number generator consists of one toggle flip flop and one and gate. A prototype random number generator is designed by logic cells based on a 2.5-kA/cm2 Nb/AlOx/Nb integration process. The fundamental operation at a few hundred megahertz of the random number sampling frequency is confirmed by numerical simulation when a DC/SFQ converter is used for generating trigger signals. An additional delay line using an overdamped Josephson transmission line is used for increasing the timing jitter to get random numbers. The delay line makes it possible for the random number generator to operate over 1 GHz. To confirm the fundamental operation of the circuit, a primitive SFQ random number generator is fabricated using the AIST standard process with 2.5-kA/cm2 Nb/AlOx/Nb junctions and the standard logic cell library. A random number generation based on a low-speed functional test is successfully confirmed.

Optical chaotic flip-flop operations with multiple triggering under clock synchronization in the VCSEL with polarization-preserved optical injection.

We investigate the evolution of nonlinear dynamic behaviors of two polarization components (x-PC and y-PC), as well as the interplay of polarization bistability and injection strength in the vertical-cavity surface-emitting laser (VCSEL) with polarization-preserved optical injection. We explore a new threshold mechanism to judge two logic outputs encoded in different dynamic behaviors of the x-PC and y-PC emitted by the VCSEL with polarization-preserved optical injection. We demonstrate implementations of two parallel optical chaotic reset-set flip-flop operations and two parallel chaotic toggle flip-flop operations that are synchronized by a clock signal and response for as short as 1 ns bit time. We further observe the reconfiguration of these two kinds of flip-flop operations with clock synchronization in different time periods by controlling the duration-time of the reset (toggle) signal with high-level. The probability of the correct trigger responses for these two kinds of flip-flop operations is controlled by the interplay of the duration-time of the reset (toggle) signal and the noise strength of the spontaneous emission. The probability that is equal to 1 for the reset-set flip-flop operations occurs in the long duration-time of the reset (toggle) signal ranging from 480 ps to 592 ps. The probability with 1 for the toggle flip-flop operations takes place in the short duration-time between 116 ps and 170 ps. Moreover, these two kinds of flip-flop operations have strong robust to the spontaneous emission noise. The optical chaotic flip-flop operation device with clock synchronization and reconfigurable trigger function proposed in our scheme offers interesting perspectives for applications where noise is unavoidable and synchronized multiple triggering is required.

Enhanced Efficiency of Electrostatically Actuated Bistable Microswitches Using Bow-Like Operation

To induce snap-through (ST) switching in an electrostatically actuated bistable latchable curved microbeam, a close gap electrode facing the concave surface of the beam is commonly used. In the framework of an alternative architecture considered here, the electrode is placed in front of the convex (backward), rather than concave (forward) side of a beam. The initially curved stress free beam is activated by an electrostatic force pulling it quasistatically in the backward direction, away from the desired buckled configuration. Once the voltage is turned off , the accumulated strain energy is released, and the beam is catapulted toward the buckled state, similarly to an arrow fired by a bow. In the case where the beam exhibits latching, the device may remain in its buckled state indefinitely under zero voltage. The beam can also be snapped back (released), by applying a voltage to the same electrode. In this article, the efficiency of this bow-like actuation is estimated. By means of a reduced order model, it is shown that due to the nonlinearity of the electrostatic force, the suggested operation scenario may lead to a 54 ${\%}$ reduction in the ST switching voltage, when compared to the traditional forward actuation. As a result, the device allows bidirectional switching by using a single electrode, and can be viewed as a micromechanical realization of a toggle flip-flop element.

In-memory designing of Delay and Toggle flip-flops utilizing Memristor Aided loGIC (MAGIC)

‘Computations inside Memory’ has become a latest area of research as ‘memory with computing skills’ accelerates the chances of developing ‘beyond-Von Neumann machines’, that is believed to be advantageous in terms of performance and energy-efficiency. ‘Memristors’ are considered as potential devices for building such memories, as they are highly dense, non-volatile scalable devices with faster switching times and lower energy dissipation and are also compatible with the existing CMOS-technology. Additionally, memristors fit in crossbar structure and can perform logic-computations, when different voltages are applied across them. Previously, various synthesis works have been reported for logic realization using memristors. But logic blocks, implemented using synthesis tools, are not always completely optimized. In this context, we present the alternative memristive-designs for the two most commonly used digital units—Delay (D) and Toggle (T) flip-flops. The proposed designs are based on Memristor Aided loGIC (MAGIC) design style and are specific to crossbar-based pure memristive-memories. A relevant simulation methodology is presented for simulating the proposed MAGIC-designs of D and T flip-flops in Cadence Virtuoso. Comparison with the existing designs of D, T flip-flops (using IMPLY) revealed that both the proposed D, T flip-flops are more performance-efficient (by 28.571%, 20% respectively) and more energy-efficient (by 83.873%, 82.905% respectively) than their corresponding IMPLY-peers. Also, the proposed D, T flip-flops are found to use reduced crossbar areas (by 46.667%, 45% respectively) relative to their counterparts generated using a recent synthesis technique, which makes the designs suitable for massive parallel executions inside memristive-memories of any size.

Design and Demonstration of Interface Circuits Between Rapid Single-Flux-Quantum and Adiabatic Quantum-Flux-Parametron Circuits

We investigated interface circuits between rapid single-flux-quantum (RSFQ) circuits and adiabatic quantum-flux-parametron (AQFP) circuits for a high-speed and low-power hybrid computing system. In addition, the interface circuits allow us to use long-distance interconnections based on single-flux-quantum (SFQ) passive transmission lines between AQFP gates. The target frequency of interface circuits is several gigahertz. There are two types of interface circuits. The RSFQ/AQFP interface circuit, which transmits a signal from RSFQ circuits to AQFP gates, was realized by coupling an RSFQ toggle flip-flop (TFF) to an AQFP buffer gate. The simulated bias margins of the RSFQ TFF and the excitation current margin of the RSFQ/AQFP interface were 2.22 mA ± 24.7% and 1.71 mA ± 25.0%, respectively. The AQFP/RSFQ interface circuit, which transmits a signal from AQFP gates to RSFQ circuits, was designed by using a high-sensitive magnetically coupled dc/SFQ converter (MC-dc/SFQ) to detect an output current of an AQFP buffer gate. The simulated bias margins of the MC-dc/SFQ and the excitation current margin of the AQFP/RSFQ interface were 0.558 mA ± 20.5% and 1.95 mA ± 36.1%, respectively. We also fabricated and measured the interface circuits.

Generation of synchronized picosecond pulses by a 1.06-µm gain-switched laser diode for stimulated Raman scattering microscopy.

We propose that a gain-switched laser diode (GS-LD) can be used as a picosecond laser source for stimulated Raman scattering (SRS) microscopy. We employed a 1.06-µm GS-LD to generate ~13-ps pulses at a repetition rate of 38 MHz and amplified them to >100 mW with Yb-doped fiber amplifiers. The GS-LD was driven by 200-ps electrical pulses, which were triggered through a toggle flip-flop (T-FF) so that the GS-LD pulses were synchronized to Ti:sapphire laser (TSL) pulses at a repetition rate of 76 MHz. We found the timing jitter of GS-LD pulses to be approximately 2.7 ps in a jitter bandwidth of 7 MHz. We also show that the delay of electrical pulses can be less sensitive to the optical power of TSL pulses by controlling the threshold voltage of the T-FF. We demonstrate the SRS imaging of polymer beads and of HeLa cells with GS-LD pulses and TSL pulses, proving that GS-LD is readily applicable to SRS microscopy as a compact and stable pulse source.

Low-Power Digital Gates in ERSFQ and nSQUID Technology

We designed and tested low-power digital gates based on the energy-efficient rapid single flux quantum (ERSFQ) and on the reversible nSQUID logic. The ERSFQ circuit consists of a series of 13 toggle flip-flops (TFFs), where the bias resistors are replaced by inductors which generate no energy dissipation in the static mode, resulting in a power consumption orders of magnitude below that of traditional RSFQ circuits during operation. The ERSFQ circuits were fabricated with HYPRES' standard 4.5-kA/cm2 process and tested up to 20 GHz. The RF input level was about −25 dBm 50 $\Omega$ matched, and the output level was 400 $\mu\text{Vpp}$ . The nSQUID ring with “NOT” gates was fabricated with HYPRES' standard 1-kA/cm2 process. The “0” and “1” input logic signals were realized injecting ±5 mA of current in a superconductive coil, obtaining 6 $\mu\text{Vpp}$ of amplitude as output signal. The test was performed at low frequency in order to verify the functionality and the ultralow power consumption.

Improved <inline-formula> <tex-math notation="TeX">$\hbox{All-MgB}_{2}$</tex-math></inline-formula> Toggle Flip-Flop Circuit With Increased Operating Speed and Temperature Range

We have fabricated and tested rapid single flux quantum toggle flip-flop circuits using self-shunted MgB 2 / MgO/MgB 2 Josephson junctions with a single ground layer. The MgB 2 films were deposited using HPCVD, and the MgO barrier was deposited using DC reactive sputtering. We highlight the circuit's voltage divider operation dependence on current bias and temperature which show operation from 7 to 30 K. The highest attained operating speed is 335 GHz at 7 K. These results demonstrate the versatile temperature range and speed of MgB 2 digital circuits.

Design and test of asynchronous eSFQ circuits

We designed and tested new energy-efficient single flux quantum (eSFQ) circuits. The eSFQ design approach is based on biasing logic gates via decision-making pairs (DMPs) which connect clock lines to synchronous gates. The eSFQ design of asynchronous gates is more challenging, since these gates are not clocked. We demonstrate eSFQ designs of asynchronous circuits and implemented two versions of eSFQ toggle flip-flops (eTFF) cells embedded in a synchronous shift register environment. The first design is based on the bias-free version of a TFF operating in the ballistic mode. In the second design, the TFFs dc bias is applied symmetrically, while the necessary half-quantum phase skew is achieved by magnetic flux bias, which can also be done with a pi-junction phase shifter. Surrounding shift registers are the eSFQ versions of the RSFQ shift register with two junctions per bit. In this work, we report the functional operation of these eSFQ circuits and their energy consumption.

All-Optical Toggle Flip-Flop Based on Monolithic Semiconductor Ring Laser

A novel monolithic all-optical flip-flop of the toggle type with two complementary outputs is demonstrated based on a semiconductor ring laser (SRL), where the intrinsic directional bistability of the SRL device is combined with the saturable absorption effect that takes place in the reverse-biased input waveguides. Toggle flip-flop (TFF) operation is experimentally demonstrated using optical trigger toggle pulses of 500 ps duration. The achieved bit-rate of 500 Mb/s is the highest reported so far for all-optical TFFs. The operational speed is limited by the carrier recovery time of the saturable absorbers; however, the proposed technology has potential for multi-gigabits per second operation.

A 36 GHz CIFF-TFF Dynamic Frequency Divider Using GaAs HBTs

A clock-inverter feed-forward toggle flip-flop (CIFF-TFF) based ultra-high-speed 2:1 dynamic frequency divider is designed in a GaAs heterojunction bipolar transistor (HBT) technology with fT of 60 GHz from Win Semiconductors corporation. The co-simulation methodology of electromagnetic field and schematic diagram is utilized in the design. Through tuning the currents in the core and the other parts of the divider separately, the dynamic frequency divider approaches an operating speed of 36 GHz with a power consumption of 162 mW in the core part from a single 6 V supply. The design is currently taped out.

Superconducting MgB2 rapid single flux quantum toggle flip flop circuit

Using self-shunted MgB2/MgO/MgB2 Josephson junctions, we have designed, fabricated, and tested a rapid single flux quantum toggle flip flop (TFF) circuit. The junctions used MgB2 films grown by hybrid physical-chemical vapor deposition with MgO barrier layer and insulating layer deposited by RF magnetron sputtering. The result showed the frequency-division function of the TFF circuit, evidenced by the output voltage being half the input voltage, up to 63 GHz at 20 K and 180 GHz at 3.2 K, which demonstrates the potential of high operating speeds and high working temperatures in MgB2 superconducting integrated circuits.

20-GHz 8 $\times$ 8-bit Parallel Carry-Save Pipelined RSFQ Multiplier

We will discuss the microarchitecture, design, and testing of the first 8 × 8-bit (by modulo 256) parallel carry-save RSFQ multiplier implemented using the ISTEC 10- kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> 1.0-μm fabrication technology. Partial products are asynchronously generated and sent to the reduction stage at the internal “hardwired” rate of 80 GHz. The 8 × 8-bit RSFQ multiplier uses a two-level parallel carry-save reduction tree that significantly reduces the multiplier latency. The 80-GHz carry-save reduction is implemented with asynchronous data-driven wave-pipelined [4:2] compressors built with toggle flip-flop cells. The design has mostly regular layout with both local and global connections between modules. The multiplier core (without SFQ-to-DC and DC-to-SFQ converters) has 5948 Josephson junctions occupying the area of 3.5 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The multiplier is designed with the target operation frequency of 20 GHz and has the latency of 447 ps at the bias voltage of 2.5 mV. Despite some challenges due to fabrication process parameter variations and flux trapping, the multiplier chip was fabricated and successfully tested for the vast majority of test vectors by the Stony Brook designers with the assistance of colleagues from Yokohama National University in February 2012. While multiplier test operations were generated at low frequency, each of these operations was executed at the “hardwired” rate of 80 GHz. The fabricated chip operated with the measured DC bias margins of ±5%.

Design and Analysis of Genetically Encoded Counters

The ability to store and to act upon modest amounts of information within living systems would enable new approaches to the study and control of biological processes. We develop a hierarchical composition framework supporting the design and analysis of higher-order genetically encoded information storage systems using combinatorial counters as a test case. We first develop a set-reset latch design based on DNA inversion, a toggle flip-flop design based upon two set-reset latches having gated outputs, and an N-bit 2N state counter design built from N toggle flip-flops. Using computational modeling, we then show how increasing the output gating speed of set-reset latches extends the operable ranges of toggle flip-flops with respect to set-reset latch switching thresholds and toggle flip-flop input pulse height and frequency. Finally, we show how coupling of input/output operable ranges of toggle flip-flops determines the operable ranges of counters. Such frameworks support the comparative analysis of competing low-level designs and further enable engineers to make the best use of limited genetic components while avoiding unnecessary compositional failure.

Design and Operation of 64-Fold Variable Single-Flux-Quantum Pulse-Number Multiplier

One of the unique applications of the single-flux-quantum (SFQ) circuitry is a digital-to-analog converter (DAC) with fundamental accuracy based on the Josephson effect. Recently, we have proposed a DAC based on frequency modulation of the output SFQ pulse train. A variable SFQ pulse-number multiplier (PNM) is a key component for the frequency-modulation DAC. In this paper, we report our design and test of a variable PNM in which the multiplication factor is determined by the sum of selected SFQ trains coming from a series array of toggle flip-flops. A 64-fold variable PNM is designed and tested using chips based on Nb. The low-speed test shows its correct functions of variable multiplication of one- to 64-fold. The high-speed test demonstrates the operation of output SFQ repetition frequency up to 0.82 GHz for 64-fold multiplication.