Toggle Flip-flop Research Articles

Improved operation range of digital superconductive electronics by implementing passive phaseshifters

We implemented small superconducting loops containing a frozen single flux quantum in single flux quantum (SFQ) electronics. Such an element acts as a π-phaseshifter which is the missing complementary circuit element in SFQ electronics and can significantly improve the circuit reliability and robustness. We designed a four bit ripple counter including toggle flip-flops (TFF) with these π-phaseshifters. We analyzed the circuit stability by means of bit error rate (BER) measurements versus bias supply. The measured operation range of the counter in standard SFQ technique was ±14% and could be improved to ±24% for the new version utilizing π-phaseshifters. These results are a clear proof for a more robust circuit realization achieved without any additional power consumption. Furthermore, it supports the reduction of present power consumption in SFQ circuits by using smaller switching energy as well as the development of more complex circuits because of a reduced sensitivity against technological parameter spread.

A single flux quantum circuit with a ferromagnet-based Josephsonπ-junction

We report on the functionality of a Nb-based superconducting singleflux quantum (SFQ) toggle flip-flop (TFF) circuit, comprising acomplementary superconductor–ferromagnet–superconductor (SFS) Josephsonπ-junction. The SFS junction was used as a phase shifting element inserted in the storage loop of theTFF. The fabricated circuits demonstrated correct functionality with the operation parameter ranges of ± 20%. The applicationof SFS π-junctions makes the SFQ circuits very compact, may substantially improve theirstability, and may also be suitable for integration with Josephson quantum circuits(qubits).

100 GHz Demonstrations Based on the Single-Flux-Quantum Cell Library for the 10 kA/cm2 Nb Multi-Layer Process

A single flux quantum (SFQ) logic cell library has been developed for the 10kA/cm 2 Nb multi-layer fabrication process to efficiently design large-scale SFQ digital circuits. In the new cell library, the critical current density of Josephson junctions is increased from 2.5 kA/cm 2 to 10 kA/cm 2 compared to our conventional cell library, and the McCumber-Stwart parameter of each Josephson junction is increased to 2 in order to increase the circuit operation speed. More than 300 cells have been designed, including fundamental logic cells and wiring cells for passive interconnects. We have measured all cells and confirmed they stably operate with wide operating margins. On-chip high-speed test of the toggle flip-flop (TFF) cell has been performed by measuring the input and output voltages. The TFF cell at the input frequency of up to 400 GHz was confirmed to operate correctly. Also, several fundamental digital circuits, a 4-bit concurrent-flow shift register and a bit-serial adder have been designed using the new cell library, and the correct operations of the circuits have been demonstrated at high clock frequencies of more than 100 GHz.

Operation of Toggle Flip-Flop Circuits Up to 500 GHz Based on Vertically-Stacked High-Temperature Superconductor Josephson Junctions

We report a developed single-flux-quantum (SFQ) circuit fabrication process for vertically-stacked interface-treated Josephson junctions by using high-temperature superconductor (HTS) and also report the 500 GHz operation of a toggle flip-flop (TFF). As the first trial of the circuit operation, we fabricated TFF circuits, because TFF is used as a benchmark circuit to indicate potential of the circuit operating speed. To develop the circuit fabrication process, we utilized the counter YBCO layer as a wiring layer. We obtained resistively-shunted-junction behavior of single junction fabricated by new process. In addition, we observed current-voltage characteristics at the input port and the output port of the TFF, and confirmed that the input voltage coincided with twice the output voltage up to 1.1 mV at 4.2 K, which corresponds to the correct operation up to 500 GHz. This frequency is the highest value in HTS circuits ever observed, which suggests the high potential of the vertically-stacked JJs for the circuit operation.

Design and implementation of cryogenic semiconductor amplifiers as interface between RSFQ circuits

Rapid single flux quantum (RSFQ) circuits create high interest in cryogenic amplifiers as interface to commercial room temperature electronics. The requirements for the amplifiers are an extremely high bandwidth (SFQ pulses with t rise = t fall = 10 ps ), high voltage gain of about 10 4 (common RSFQ output voltage level of about 200 μ V ), low power consumption (cryogenic environment at 4 K) and low noise. Hybrid amplifiers, based on commercial available p-HEMT transistors, can solve the problematic high-speed interface. In this paper, we present measurement results of a hybrid four stage coplanar amplifier in combination with a RSFQ Toggle Flip-Flop (RSFQ T-FF) and a Josephson array quantizer (JA-Q).

Advances in High-Tc Single Flux Quantum Device Technologies

We have developed the fabrication process, the circuit design technology, and the cryopackaging technology for high-T c single flux quantum (SFQ) devices with the aim of application to an analog-to-digital (A/D) converter circuit for future wireless communication and a sampler system for high-speed measurements. Reproducibility of fabricating rampedge Josephson junctions with I c R n products above 1 mV at 40 K and small I c spreads on a superconducting groundplane was much improved by employing smooth multilayer structures and optimizing the junction fabrication process. The separated base-electrode layout (SBL) method that suppresses the J c spread for interface-modified junctions in circuits was developed. This method enabled low-frequency logic operations of various elementary SFQ circuits with relatively wide bias current margins and operation of a toggle-flip-flop (T-FF) above 200 GHz at 40 K. Operation of a 1:2 demultiplexer, one of main elements of a hybrid-type Σ-△ A/D converter circuit, was also demonstrated. We developed a sampler system in which a sampler circuit with a potential bandwidth over 100 GHz was cooled by a compact stirling cooler, and waveform observation experiments confirmed the actual system bandwidth well over 50 GHz.

Low-noise RSFQ circuits for a Josephson Qubit control

We address the problem of reducing the noise of an RSFQ circuit, which may significantly decohere a Josephson qubit in the case of integration of these circuits. The main sources of such noise in traditional RSFQ circuits are low-ohmic shunting resistors ensuring sufficiently high damping. We developed the toggle flip-flop (TFF) cells with weakly-damped individual junctions due to high-ohmic shunts. The dominant part of necessary damping in this circuit was realized by applying an additional, so-called ‘perpendicular’, low-ohmic resistor connecting the centre of the storing TFF inductance to ground. The TFF circuits with junctions shunted by 50 Ω resistors and perpendicular resistor of 1.5 Ω, ensuring suppression of noise by more than one order, have been fabricated and demonstrated an operation range of ±20%. In order to make the circuit compact and, therefore, less sensitive to external noise, the passive frozen-flux-based phase shifting elements, replacing large quantizing inductances, were also included. The circuits were fabricated using PTB Nb trilayer process with critical current density jc = 100 A/cm2.

Design and Operation of HTS SFQ Circuit Elements

Single flux quantum (SFQ) circuit elements have been designed and fabricated using the YBa 2 Cu 3 O 7-δ ramp-edge junction technology. Logic operations of SFQ circuit elements, such as a toggle flip-flop (T-FF), a set-reset flip-flop (RS-FF), and a 96-junction Josephson transmission line (JTL), were successfully demonstrated, and dc supply current margins were confirmed up to temperatures higher than 30 K. The circuit layout was improved in order to suppress the critical current (I c ) spread that appears during the junction fabrication procedure. By employing the new circuit layout rule, correct operations at temperatures from 27 K to 34 K with dc supply current margins wider than ±7% were confirmed for the T-FF with a single output. Moreover, the maximum operating frequencies of T-FFs were measured to be 360GHz at 4.2K and 210GHz at 41K, which are substantially higher than the values for the circuits with the conventional layout. According to the simulation result, the maximum operating frequency at 40 K was expected to be approximately 50% of the characteristic frequency at a bit error rate (BER) less than 10 -6 .

Microfluidic Bubble Logic

We demonstrate universal computation in an all-fluidic two-phase microfluidic system. Nonlinearity is introduced into an otherwise linear, reversible, low-Reynolds number flow via bubble-to-bubble hydrodynamic interactions. A bubble traveling in a channel represents a bit, providing us with the capability to simultaneously transport materials and perform logical control operations. We demonstrate bubble logic AND/OR/NOT gates, a toggle flip-flop, a ripple counter, timing restoration, a ring oscillator, and an electro-bubble modulator. These show the nonlinearity, gain, bistability, synchronization, cascadability, feedback, and programmability required for scalable universal computation. With increasing complexity in large-scale microfluidic processors, bubble logic provides an on-chip process control mechanism integrating chemistry and computation.

Study on the optical input interface for Nb single-flux-quantum logic circuits

The authors have studied the optical input interface for Nb single-flux-quantum (SFQ) circuits and demonstrated its operation using photomixing technique. Two tunable lasers of C band were used for photomixing. We adopted a multistage toggle flip-flop (TFF) circuit as the main part of the test circuit. As the first trial, we used lasers with wavelength difference of 0.044nm at around 1550nm, which corresponds to the laser beat frequency of 5.5GHz. The output signals from the 13- and 14-stage TFFs were observed and it showed the input SFQ frequency of 5.5GHz. Thus, the authors demonstrated the conversion of the optical signal to SFQ signal and succeeded in driving the SFQ circuit.

Operation of HTS Toggle-Flip-Flop Circuit With Improved Layout Design

Toggle-flip-flop (T-FF) is one of the most important high-T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c </sub> superconducting single-flux quantum (HTS SFQ) circuit components and has been designed and fabricated by using YBa <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> Cu <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3 </sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7-delta</sub> ramp-edge junction technology. The circuit layout of the T-FF was improved to suppress the junction critical current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> ) spread in the circuit. Test circuits, which include a T-FF with a single output for evaluating the logic operation and measuring the operating frequency, were fabricated and their operation characteristics were investigated. The T-FF circuit with a single output was successfully operated and finite direct current (dc) supply current margins were obtained at temperatures from 27 to 34 K. Moreover, the maximum operating frequency of the T-FF was estimated to be 360 GHz at 4.2 K and 114 GHz at 41 K. In addition, reduction of dc supply current margins due to thermal noise was also investigated. According to the numerical simulation in which parasitic inductances were taken into account, the narrowest margin in the T-FF circuit wider than plusmn10% was maintained with a bit-error rate (BER) of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-6 </sup> up to 40 K

Dynamics of Josephson junctions and single-flux-quantum networks with superconductor–insulator–normal-metal junction shunts

Within the framework of the microscopic model of tunneling, we modelled the behavior of the Josephson junction shunted by the Superconductor-Insulator-Normal metal (SIN) tunnel junction. We found that the electromagnetic impedance of the SIN junction yields both the frequency-dependent damping and dynamic reactance which leads to an increase in the effective capacitance of the circuit. We calculated the dc I-V curves and transient characteristics of these circuits and explained their quantitative differences to the curves obtained within the resistively shunted junction model. The correct operation of the basic single-flux-quanta circuits with such SIN-shunted junctions, i.e. the Josephson transmission line and the toggle flip-flop, have also been modelled.

On-chip microwave generator for manipulation of superconductive quantum bits

A new on-chip microwave generator for manipulating superconductive quantum bits (qubits) have been proposed. To perform practical quantum computation, on-chip microwave generators, which can be controlled by single flux quantum (SFQ) circuits, are desirable because multiple qubits can be driven simultaneously with high accuracy by an SFQ control circuit and the number of wires between qubits and room-temperature electronics can be reduced. The proposed on-chip microwave generator is composed of an SFQ clock generator, which generates a periodic SFQ pulse train, and a band-pass filter. A sinusoidal microwave can be obtained by filtering an output of the SFQ clock generator. Simulation results indicate that the generated microwave has a sharp spectrum, which can be chopped by controlling the SFQ clock generator. Moreover, a phase of the generated microwave can be accurately controlled by adding a phase control circuit, which is composed of cascaded toggle flip-flops, between the SFQ clock generator and the filter. The results indicate that we can perform fast and accurate quantum gate operations using the proposed on-chip microwave generator.

Toggle-flip-flop operation in oxide SFQ circuit

Toggle-flip-flop (T-FF), that is one of the most important oxide single flux quantum (SFQ) circuit elements, was designed and fabricated, and its logic operation was examined. For widening junction critical current (Ic) margins, it was found effective to decrease Ic values in the T-FF cell much less than those of junctions in Josephson transmission lines (JTLs). A T-FF test circuit with a single output and that with two outputs were fabricated based on the YBa2Cu3O7−δ ramp-edge junction technologies. T-FF operations of the fabricated circuits were successfully performed at low frequencies. In particular, finite operating margins for the T-FF with two outputs were obtained at 35K.

Fabrication of high-temperature superconductor single-flux-quantum circuits using amultilayer structure with a smooth surface

We have developed a multilayer structure with a smooth surface and fabrication processes forHTS single-flux-quantum (SFQ) circuits. The multilayer structure with surface roughnessRa less than 2 nm,composed of a La0.2–Y0.9Ba1.9Cu3Ox ground plane and base electrode layer, andSrSnO3 insulating layers, was deposited by off-axis magnetron sputtering. We havefabricated interface-engineered junctions based on the multilayer structure using anLa0.2–Yb0.9Ba1.9Cu3Ox counter-electrode layer prepared by pulsed laser deposition. Thefabricated junctions exhibited excellent Josephson characteristics with a1-σ spread in Ic as low as 8% for 1000 junctions. The sheet inductance values below 50 K were 0.8–1.0 pHper square. Operation of several elementary SFQ circuits including a toggle flip-flop, aconfluence buffer, a set–reset flip-flop and other SFQ elements has been successfullydemonstrated at 30–60 K.

Single-ended frequency divider with moduli of 256–271

This paper demonstrates a low-cost 2.4 GHz single-ended frequency divider with the divide-by-value from 256 to 271 in the standard 0.35-μm 2P4M CMOS technology. This frequency divider is composed of a synchronous current mode logic divide-by-4/5 prescaler, an asynchronous true single-phase-clock toggle flip-flops divide-by-64 divider, and a digital control circuitry. This proposed divider is single-ended and compatible to the single-ended low-phase-noise Colpitts VCO. The operating frequency range of the divider is from 400 to 2.9 GHz. Most of the input sensitivity levels are about −10 dBm and the lowest level is −25 dBm at 2.4 GHz. Its core power consumption is about 28 mW. The chip size is 1.2 × 0.7 mm2. © 2006 Wiley Periodicals, Inc. Microwave Opt Technol Lett 48: 2096–2100, 2006; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.21876

An All-Digital CMOS Duty Cycle Correction Circuit with a Duty-Cycle Correction Range of 15-to-85% for Multi-Phase Applications

An all-digital CMOS duty cycle correction (DCC) circuit with a fixed rising edge was proposed to achieve the wide correction ranges of input duty cycle and PVT variations, the low standby power and the fast recovery from the standby mode for use in multi-phase clock systems. SPICE simulations showed that this DCC adjusts the output duty cycle to 50 ± 0.7% for the wide range of input duty cycle from 15% to 85% at the input frequency of 1 GHz, within the commercial range of PVT corners. The all-digital implementation and the use of a toggle flip flop at the input stage enabled the wide correction ranges of PVT variations and input duty cycle, respectively.

Superconductor integrated circuit fabrication technology

Today's superconductor integrated circuit processes are capable of fabricating large digital logic chips with more than 10 K gates/cm/sup 2/. Recent advances in process technology have come from a variety of industrial foundries and university research efforts. These advances in processing have reduced critical current spreads and increased circuit speed, density, and yield. On-chip clock speeds of 60 GHz for complex digital logic and 750 GHz for a static divider (toggle flip-flop) have been demonstrated. Large digital logic circuits, with Josephson junction counts greater than 60 k, have also been fabricated using advanced foundry processes. Circuit yield is limited by defect density, not by parameter spreads. The present level of integration is limited largely by wiring and interconnect density and not by junction density. The addition of more wiring layers is key to the future development of this technology. We describe the process technologies and fabrication methodologies for digital superconductor integrated circuits and discuss the key developments required for the next generation of 100-GHz logic circuits.

50-Gbit/s InP HEMT 4 : 1 multiplexer/1 : 4 demultiplexer chip set with a multiphase clock architecture

A 50-Gbit/s InP high electron-mobility transistor (HEMT) chip set of 4 : 1 multiplexer (MUX) and 1 : 4 demultiplexer (DMUX) integrated circuits (ICs) with a multiphase clock (MPC) architecture is described. The MPC architecture employs a quarter-rate four-phase clock generated by a toggle flip-flop inside the ICs, which reduces the number of circuit elements and lowers the power consumption. The fabricated 4 : 1 MUX and 1 : 4 DMUX ICs exhibited 50-Gbit/s error-free operations for 2/sup 31/-1 pseudorandom bit sequences with 1.71- and 1.42-W power consumption, respectively. Compared to conventional tree-type 4 : 1 MUX and 1 : 4 DMUX ICs using InP HEMTs, the MPC 4 : 1 MUX and 1 : 4 DMUX ICs operate at the same operating speed with less than one-third power consumption.

Rapid single-flux quantum logic using π-shifters

We have found that the size of some rapid single-flux quantum (RSFQ) logic cells based on conventional 0-type Josephson junctions can be significantly reduced by using a π-type junction as a phase shifter in passive (nonswitching) mode. In comparison with the recently suggested active (switching) π-junctions mode, the passive mode offers much greater operation margins for their critical current Icπ. This gives π-junctions a chance to be implemented in RSFQ designs in the near future. As an example, we have simulated the operation of a toggle flip flop with zero-geometrical inductance of the fluxon storage loop. Simulations show that the parametric inductance of the π-junction and its normal resistance Rn form a low-pass filter, which sets the low limit for π-junctions IcπRn product, but offers a wide range of variations of the other parameters. The possible reduction of RSFQ cell size by using π-junctions opens the way to scale superconducting logic circuits down to the submicron dimensions.