Toggle Flip-flop Research Articles

Single flux, quantum B flip-flop and its possible applications

We are introducing a new subfamily of rapid single-flux-quantum (RSFQ) digital cells, based on a single B flip-flop template. The template can be considered as an SFQ flip-flop with up to 4 inputs and 6 outputs. Each input SFQ pulse can change the flip-flop's internal state. Each output presents (in the form of SFQ pulses a specific logic function of the initial state of the cell and input signals. Simple connection of various inputs and/or outputs, combined with shortening or opening of certain branches of the template allows one to implement a variety of RSFQ cells with wide margins. Of these various RSFQ cells, we have designed and successfully tested the T1 cell (asynchronous toggle flip-flop with synchronous destructive readout), single-bit full adder, and single-bit stage of an up-down counter. Experimentally measured margins for dc power supply voltage for these circuits were /spl plusmn/24%, /spl plusmn/24%, and /spl plusmn/17%, respectively.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Simulation and optimization of binary full-adder cells in rapid single flux quantum logic

The authors consider the design of a binary carry full-adder cell using the logic gates and buffers belonging to the rapid single-flux-quantum (RSFQ) logic family. They have taken advantage of the unique properties of RSFQ pulse logic to realize two designs: one using two logic gates and a toggle flip-flop in two stages of logic, the other using two logic gates in one stage of logic. They have determined the parameter margins of the two full-adder cells and optimized them to obtain critical margins approaching +or-30%. Simulations of the full-adder cells have revealed critical delays and maximum clock frequencies of 58 ps and 17 GHz and 33 ps and 30 GHz, respectively.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

20 Gb/s digital SSIs using AlGaAs/GaAs heterojunction bipolar transistors for future optical transmission systems

Design principles for achieving good eye opening and circuit optimization to extract high performance from AlGaAs/GaAs heterojunction bipolar transistor (HBT) devices are described. Using the circuit techniques and HBTs with an f/sub T/ of 70 GHz and an f/sub max/ of 50 GHz, four kinds of SSIs are developed for future optical transmission systems. High-bit-rate operation of over 20 Gb/s (26 GHz toggle flip-flop, 20 Gb/s decision circuit, 20 Gb/s EXCLUSIVE OR/NOR gate, and 28 Gb/s selector IC), extremely fast rise and fall times (20-80%) of 20 and 14 ps, respectively, and good eye opening are obtained. In addition, potential performance gains that might be realized through advanced circuit and device design are appraised, and throughputs as fast as 40 Gb/s are predicted.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Analysis and Synthesis of Asynchronous Sequential Networks Using Edge-Sensitive Flip-Flops

Standard flow table methods for analysis and synthesis of asynchronous sequential switching networks are difficult to apply when edge-sensitive flip-flops are used. Use of a differential mode (DM) state table, which specifies the next state as a function of the present state and input change, avoids such difficulties. Difference operators, which are used to specify changes in logic variables, provide a convenient means for defining terminal behavior of edge-sensitive flip-flops. The inhibited toggle flip-flop is introduced as a general-purpose edge-sensitive flip-flop. Sequential networks are analyzed by writing difference operator equations from which a DM table can be constructed. Synthesis of asynchronous networks is accomplished by first constructing a DM table to describe the desired network and then deriving input equations for inhibited-toggle flips-flops. Such realizations are free of hazards and critical races and usually require fewer gates and flip-flops than solutions by standard flow table methods.