Design and test of asynchronous eSFQ circuits

Abstract

We designed and tested new energy-efficient single flux quantum (eSFQ) circuits. The eSFQ design approach is based on biasing logic gates via decision-making pairs (DMPs) which connect clock lines to synchronous gates. The eSFQ design of asynchronous gates is more challenging, since these gates are not clocked. We demonstrate eSFQ designs of asynchronous circuits and implemented two versions of eSFQ toggle flip-flops (eTFF) cells embedded in a synchronous shift register environment. The first design is based on the bias-free version of a TFF operating in the ballistic mode. In the second design, the TFFs dc bias is applied symmetrically, while the necessary half-quantum phase skew is achieved by magnetic flux bias, which can also be done with a pi-junction phase shifter. Surrounding shift registers are the eSFQ versions of the RSFQ shift register with two junctions per bit. In this work, we report the functional operation of these eSFQ circuits and their energy consumption.