TiW Barrier Layer Research Articles

The Influence of Tiw Barrier Layer on Reliability of AlCu and AlSiCu Interconnects

AbstractThe influence of a TiW barrier layer on the stress-voiding behavior of AlCu and AlSiCu interconnects is investigated. The results are compared to the same alloys deposited on SiO2- In both cases, AlCu exhibits a notably better voiding behavior compared to AlSiCu. In the case in which the alloys are directly deposited on the TiW barrier without breaking vacuum between TiW and Al(Si)Cu depositions, a significant improvement of the voiding behavior of both alloys is observed. Compared to AlCu, AlSiCu shows worse voiding behavior due to the presence of Si precipitates, which introduce significant extra dislocations and defects in the Al grains. These dislocations and defects are diffusion paths which assist stress relaxation and void formation. In the presence of a TiW barrier part of the Si content of the AlSiCu is consumed during the anneal by the Al-TiW interface, which results in a decreased number of dislocations and defects within the Al grains, and an improved voiding behavior compared to AlSiCu on SiO2-Furthermore, W and Ti diffuse into the grain boundaries of both alloys. The presence of W and Ti in the grain boundaries reduces the amount of Cu depletion from within the grains, which makes both alloys more resistant to stress voiding. The above is supported by Auger and TEM results. The electromigration results of the alloys in question are presented. These show that also with respect to electromigration AlCu is the preferred alloy both on TiW and SiO2.

Annealing behaviour of the specific contact layer resistivity for an Au bump-TiW-Al pad structure

The specific contact layer resistivity between gold bumps and aluminium pads with a TiW barrier layer has been determined. It is about 1.2-1.5 Omega mu m2 and increases visibly after heat treatment at temperatures greater than 350 degrees C for 1 h but only increases a little below temperatures of 350 degrees C. The processes are associated with the formation of intermetallic compounds which is governed by diffusion of metallic elements. The activation energy of the processes was determined to be 1.15 eV, which is more than that for the structures without a TiW barrier layer. The barrier function of the TiW layer has been confirmed.

Investigation of Titanium Silicide Formation Using Secondary Ion Mass Spectrometry

ABSTRACTSecondary ion mass spectrometry (SIMS) and X-ray photoelectron spectroscopy (XPS) are used to investigate Ti silicide formation mechanisms on a series of Ti on Si thin films annealed in ultrahigh vacuum (UHV) at different temperatures and durations. The competition between oxygen diffusion and the silicide formation reaction (the socalled “snowplough” effect) is observed directly, as well as a Ti-Si-O layer. The results from these controlled experiments are compared with those from Ti silicide films formed under rapid thermal annealing (RTA) conditions in a production furnace, with and without a TiW barrier layer.

Process integration, architecture and simulation of a GHz-BiCMOS ULSI technology

The integration of submicron poly-emitter transistor technology with CMOS devices, scaled down to 0·8 μm, to enhance the operating performance of BiCMOS ASICs in the GHz range, is described. It enables incorporation of npn, NMOS and PMOS transistors, Schottky diodes, polysilicon resistors and lateral fuses. The proposed process can facilitate CMOS, TTL and ECL signal levels on the same chip. To make the process more consistent and easy, the 19 masking steps are incorporated; most of them are noncritical oversized implant masks. N + and P + buried twin wells are formed for low isolation spacings along with their respective N and P epitaxial layers, to eliminate latchup susceptibility. The process includes some special features to increase the layout density and to reduce the parasitic capacitances. This is achieved by using sidewall spacers for polysilicon, self aligned vertical npn transistor structures and undoped polysilicon trench isolations. To obtain high f T (cut-off frequency) in the npn bipolar transistor, P + poly base, N + poly emitter and shallow junctions are incorporated. Titanium salicidation of N + and P + polysilicon is proposed while, on the source-drain of MOS transistors, a 20 nm thick TiW barrier layer deposition is added. A multilayer interconnect technology is employed with tungsten plugging and gold metallization. The 125-step process has been simulated for oxidation, impurity drive-in schedules and 12 implantation schemes in order to optimize various impurity profiles. The 60 nm emitter junction depth and 160 nm base width have been controlled by mixed boron and arsenic ion implantation through a poly-emitter window. The profile of an npn bipolar device, generated by process simulator (SUPREM), is directly provided to the device simulator (SEDAN) to find various important dc characteristics. The calculated f T and early voltage of the bipolar device were more than 7 GHz and 17 V respectively. For ac analysis of the above device, an inhouse-made high-speed transistor package (HIBTRA) has been used to explain the sinusoidal and transient behaviour of the device. The submicron MOS devices have been first simulated on an inhouse device simulator (MOSKIT) to determine their characteristics such as drain current, subthreshold current, substrate current and also to compute various MOS parameters required for circuit simulation and threshold voltage adjustment implantation doses.

Cracking Behaviour during Au‐Au TAB Inner Lead Bonding

Tape automated bonding (TAB) is an interconnection technique for integrated circuits (ICs) with a small lead pitch and a thin assembly thickness. During inner lead bonding the flying (Au plated Cu) leads of the TAB foil are connected to the Au bumps on the bondpads of an IC. The Au bumps are deposited in the openings of a thick Novolac based resist layer by electroplating. The resist is coated on a sputtered TiW‐Au metallisation; TiW is the barrier layer between Au bump and Al bondpad. Bonding of the leads to the Au bumps requires substantial plastic deformation of the bump and lead. As a result of this deformation, the TiW barrier layer underneath the bump may crack easily. A theoretical model has been used to describe the occurrence of these cracks. This theoretical model is compared with experimental results of deformation and cracking behaviour by visual inspection of the TiW barrier and the etched cross‐sections. Separate (single point) and simultaneous (gang) bonding techniques, different gold plating baths and TAB tapes are used to study the cracking behaviour.

Electrical properties of the thermal induced degradation in TiSi2/TiW/AlSi layered structures

Thermal degradation of TiSi2/TiW/AlSi layered structures is studied by the resistivity measurements on samples annealed in the temperature range of 400–550 °C. The effect of using pure TiW and stuffed TiW(N) as a diffusion barrier on the reaction kinetics of the layered structure is studied. The change in the resistivity is correlated to the rate of formation of intermetallic compound. It is shown that the reaction rate of the compound formation is reduced by about 25% for TiW(N) barrier layer compared to pure TiW annealed at 500 °C.

The effect of Si and Cu on the interactions between Al films and a TiW barrier layer

The effect of doping 1 wt % Si or 0.9 wt % Cu to Al films on the interactions between Al and TiW barrier layers at 450 °C was studied. It was found that the first product is always Al12W, which forms at the Al/TiW interface, irrespective of the dopant addition. However, doping 1 wt % Si to Al film enhances the Al12W formation while doping 0.9 wt % Cu retards its formation. With excess tungsten in the system, Al12W would further react with W to form Al/W compounds with higher W content. In pure Al film, both the hexagonal Al5W phase and the monoclinic Al4W phase were detected to form after prolonged annealing at 450 °C. The addition of 1 wt % Si or 0.9 wt % Cu to Al prohibits the formation of Al5W, thus only the Al4W phase was observed at the W/Al12W interface in the doped Al films.

Effect of copper content on reaction compound formation in Al-Cu/Ti-W bilayers

In modern integrated circuits, a barrier layer of Ti-W is commonly used to reduce interdiffusion between Al-alloy interconnects and the Si substrate for multilevel metallization. Deterioration of the metallization layers may occur by the interaction of the Al-alloy film with the Ti-W sublayer during post-metallization thermal processing, resulting in the formation of aluminide reaction compounds, such as Al12W and Al5W. The reaction morphologies of the Al film with other transition metals, such as Ti4 and Hf5, have been studied. The morphologies of the compounds are planar for Al3Ti and spiked for Al3Hf, respectively. When Cu solute is added to Al, it has a significant effect on the growth and morphology of these reaction compounds. Although Al-Cu/Ti-W films are now extensively used for multilevel metallization, the effect of Cu content on the reaction growth and morphology of the compound has not been studied in detail. In this work, we report on the effect of Cu content on the reaction between the Al-Cu layer and Ti-W barrier layer, and the resulting morphology.

The addition of Ni in AuZn gate Ohmic contacts for InP junction field effect transistors

The fabrication and characteristics of AuZn/Ni/Cr/Au and AuZn/Ni/TiW/Au gate Ohmic contacts for InP junction field effect transistors (JFET’s) are reported. Auger electron spectroscopy sputter-depth profiles reveal substantial Ni interdiffusion at the metal–InP interface after heat treatment at 410 °C. The addition of a Ni layer significantly improves the adhesion of the contacts and a TiW barrier layer effectively maintains the conductivity of the gate metallizations after heat treatment. The specific contact resistance of the JFET gate structures is measured to be as low as 2×10−5 Ω cm2, which is the lowest value reported to date for contacts to p-type InP. InP JFET gate-drain diodes fabricated with the AuZn/Ni/TiW/Au gate contact exhibit a leakage current of ∼40 nA at −8 V for a 1μm×150 μm gate and a reverse breakdown voltage of 17.5 V at 25 μA. The contacts are shallow, as evidenced by the quality of the p+/n junctions fabricated, and thus are suitable for use in InP JFET structures where thin p+ regions are utilized.

Specific contact resistivity of TiSi2to P+and n+junctions

Specific contact resistivities of the Al/TiW/TiSi 2 /Si system are characterized. It is found that without a TiW barrier layer, Al can penetrate through the TiSi 2 layer and significantly affect the TiSi 2 /Si interfacial contact resistance. Intrinsic TiSi 2 contact resistivities to n+and p+silicon are characterized with a TiW barrier between the silicide and the aluminum. TiSi 2 contact resistivity to n+silicon is found to be about one order of magnitude lower than that of Al to n+silicon. However, TiSi 2 to p+silicon contact resistivity is higher than that of Al to p+silicon and is very sensitive to the boron implant dose.

Comparative study of Nb and TiW barrier layers between Au and a-SiO2

The performance of Ti0.3W0.7 and Nb thin films as diffusion barriers for Au was investigated by Rutherford backscattering spectrometry (RBS) and Auger electron spectroscopy (AES). The films were sputter deposited in Ar:N2 (70:30 vol%) or pure Ar on amorphous SiO2. They were annealed in air at temperatures ranging from 250 °C up to 750 °C for several hours. In-depth profiles revealed an onset of oxidation of the barriers at 520 °C for Nb and about 600 °C for TiW. Barrier oxidation and extensive diffusion could be correlated. Distinct diffusion behavior as a function of temperature was established between TiW and Nb. A Nb multilayer structure was found to provide the best reliability as the barrier and as the adhesion layer.

Bipolar Schottky logic device failure modes due to contact metallurgical degradation

Failure modes of bipolar Schottky logic devices due to metallurgical degradation of PtSi/Ti-W/Al contacts were studied. Both to the purpose prepared wafers and commercial 74LSOO TTL Low-Power Schottky devices were used. Metallurgical failures are primarily due to Al diffusion through the Ti-W barrier layer. As a consequence, thermal treatments induce electrical failures which begin with a loss of fan-out followed by longer rise and fall switching times. Finally complete device failure is observed when the output stays always at the high logic level. Emitter-base leakages and short-circuits, due to Si dissolution in the overlaying metal system, can explain the observed electrical degradations which are markedly delayed by a thin oxygen layer present at the Al/Ti-W interface.