TiN Gate Electrode Research Articles

Thermal stability of TiN gate electrode for 4H-SiC MOSFETs and integrated circuits

In this research, the thermal stability of single-stage amplifiers based on a 4H-SiC MOSFET with a TiN gate electrode was investigated. The results show that after 100 h aging at 400 °C in N2 ambient, the amplifier maintained good performance with stable voltage gain. The thermal stability of the amplifier is attributed to the stability of Ni/Nb/4H-SiC source/drain ohmic contact, implanted load resistor, and MOS structure with the TiN gate electrode. The results obtained from the 4H-SiC MOS structure show that the interface trap density at the SiO2/SiC decreases during the aging process. While the gate leakage current of the capacitor based on the Al gate electrode increases, it remains stable in structures with TiN gate electrodes after 100 h aging. The results obtained in this study indicate that TiN is promising for the gate electrode of 4H-SiC MOSFETs for high-temperature applications.

Remote Oxygen Scavenging of the Interfacial Oxide Layer in Ferroelectric Hafnium-Zirconium Oxide-Based Metal-Oxide-Semiconductor Structures.

Discovery of ferroelectricity in HfO2 has sparked a lot of interest in its use in memory and logic due to its CMOS compatibility and scalability. Devices that use ferroelectric HfO2 are being investigated; for example, the ferroelectric field-effect transistor (FEFET) is one of the leading candidates for next generation memory technology, due to its area, energy efficiency and fast operation. In an FEFET, a ferroelectric layer is deposited on Si, with an SiO2 layer of ∼1 nm thickness inevitably forming at the interface. This interfacial layer (IL) increases the gate voltage required to switch the polarization and write into the memory device, thereby increasing the energy required to operate FEFETs, and makes the technology incompatible with logic circuits. In this work, it is shown that a Pt/Ti/thin TiN gate electrode in a ferroelectric Hf0.5Zr0.5O2 based metal-oxide-semiconductor (MOS) structure can remotely scavenge oxygen from the IL, thinning it down to ∼0.5 nm. This IL reduction significantly reduces the ferroelectric polarization switching voltage with a ∼2× concomitant increase in the remnant polarization and a ∼3× increase in the abruptness of polarization switching consistent with density functional theory (DFT) calculations modeling the role of the IL layer in the gate stack electrostatics. The large increase in remnant polarization and abruptness of polarization switching are consistent with the oxygen diffusion in the scavenging process reducing oxygen vacancies in the HZO layer, thereby depinning the polarization of some of the HZO grains.

Oxygen‐Scavenging Effects of Added Ti Layer in the TiN Gate of Metal‐Ferroelectric‐Insulator‐Semiconductor Capacitor with Al‐Doped HfO2 Ferroelectric Film

AbstractTi layer inserted in the TiN gate electrode effectively scavenges the oxygen in the low‐k interfacial SiO2 of the metal–ferroelectric–insulator–semiconductor (MFIS) capacitors with the ferroelectric Al‐doped HfO2 (HAO) thin film. The scavenging effect increases remanent polarization (Pr) and reduces coercive voltage (Vc) and capacitance equivalent thickness (CET) of the HAO films, particularly when the MFIS capacitor is annealed at 800 °C. Additionally, frequency dispersion of capacitance characteristics and interface trap density (Dit) calculations reveal that actively‐triggered oxygen‐scavenging effects also reduce defect or trap‐induced degradation. The Ti‐inserted MFIS structure exhibits fatigue‐free endurance and relatively low leakage current characteristics as compared to a structure without the Ti scavenging layer in high annealing temperature conditions required for crystallization of the HAO ferroelectric films.

Re-examination of effects of ALD high-k materials on defect reduction in SiGe metal–oxide–semiconductor interfaces

We study the impact of the atomic layer deposition high-k gate insulators on metal–oxide–semiconductor (MOS) interface properties of Si0.78Ge0.22 gate stacks with TiN gate electrodes and the physical origins of the reduction in MOS interface defects. The SiGe MOS interface properties of TiN/Y2O3, Al2O3, HfO2, and ZrO2 gate stacks are compared over a wide range of annealing temperatures. It is found that the lowest interface trap density (Dit) is obtained by TiN/Y2O3 stacks with post-metallization annealing (PMA) at 450 °C among the gate stacks with other gate insulators. Moreover, it is revealed that less amount of GeOx in the interfacial layer leads to lower Dit and that the Y2O3 stacks yield further reduction in Dit during PMA at 450 °C. These results can be explained by the reduction in distorted Ge–O bond densities in GeOx in ILs by scavenging and annealing effects during PMA and the suppression of Ge dangling bond generation by incorporating Y atoms into GeOx during PMA at 450 °C.

Reliability Analysis on TiN Gated NMOS Transistors

Compared to poly Si gate, metal gate has no gate depletions and experiences inversion capacitance gain, which makes an advantage for devices scaling. In this paper, we investigated the gate oxide leakage current and Time Dependent Dielectric Breakdown (TDDB) characteristics of TiN and poly Si electrodes with a 3.5 to 5 nm SiO2 dielectric thickness range. According to the Transmission Electron Microscope (TEM) analysis there is difference in oxide thickness. The SiO2 thickness of TiN gate electrode has been reduced by ~0.25 nm, considerably because of a scavenging effect. We normalized the reduced SiO2 thickness with an electrical oxide field, and there were no differences between the two electrodes in gate leakage current, accumulation breakdown voltage (BV), and accumulation TDDB lifetime. Therefore, we found the scavenging effect of TiN electrodes seems to affect little the leakage current and TDDB reliability of SiO2 dielectric. On the other hand, the BV and TDDB lifetime of TiN electrode in the inversion region are little bit better than that of the poly electrode. We think this differences are originated from the difference between TiN/SiO2 and poly Si/SiO2 interfaces.

Analog Performance of SOI nMuGFETs with Different TiN Gate Electrode Thickness and High-k Dielectrics

This work presents an analysis of the analog performance of SOI MuGFET devices and the impact of different TiN metal gate electrode thickness.Thinner TiN metal gate allows achieving large gain and this effect can be attributed to the increased Early voltage values observed for thinner TiN metal gate. This VEA increase suggests an increase of the transversal electrical field for thin TiN metal gate (reduced gate oxide thickness) that is confirmed with the increment of the GIDL current.This impact on the voltage gain is maintained for short channel length.The impact of different gate dielectrics was also studied where high-k dielectric indicated a higher VT due to a VFB variation. Additionally, lower intrinsic voltage gain was observed for hafnium dielectric and this can be related to the lower Early voltage (VEA) present in this devices.

Vertical MOS and tunnel FETs in the same silicon pillar structure with Al and TiN gate electrodes

This work presents a silicon pillar structure containing both MOS (Metal-Oxide-Semiconductor) and Tunnel Field Effect Transistors (MOSFETs and TFETs, respectively) with Al and TiN double-gate electrodes. The abrupt n+ regions of drain/source in the p-Si vertical pillar are obtained from sequential 31P+ ion implantations (energies of 100, 50 and 25 keV) and Rapid Thermal Annealing (RTA). The abrupt drain region in the p-Si pillar allows the vertical control of the channel length of the MOSFET device (achieving lengths such as 70 nm) and the formation of a nano-intrinsic region (2 nm), between n+ and p regions, fundamental for the operation of a TFET. The MOSFETs and TFETs, which were fabricated with Al gate, have presented the better results (Ion of 56 μA/μm, gm of 45 μS/μm and (Ion/Ioff) ratio of 107) related to higher performance in conduction regime. However, both devices, fabricated with TiN, have presented higher performance related to leakage and/or off current (Ioff of 1.8 pA/μm). It is important to notice that the alternating use at the same silicon pillar for the both MOSFET or TFET devices can be suitable to the applications in which are necessary high and low power operations, respectively.

Comprehensive and systematic design of metal/high-k gate stack for high-performance and highly reliable SiC power MOSFET

Aluminum-based high-permittivity (high-k) gate dielectrics and suitable metal electrodes were systematically designed for advanced SiC power metal-oxide-semiconductor field-effect transistors (MOSFETs). Although electron injection into alumina (Al2O3) was significantly suppressed by nitrogen incorporation (aluminum oxynitride: AlON), gate leakage current under negative gate bias and hole trapping into the dielectrics were observed. Adding hafnium into the AlON (HfAlON) was investigated to overcome these drawbacks, and an atomic layer deposition-based method for HfAlON was developed in terms of permittivity, energy bandgap, and hole conduction under negative stressing conditions. Consequently, the reliability of metal/high-k gate stacks under both positive and negative bias temperature stresses was improved by using an optimized HfAlON gate dielectric in combination with a high work-function TiN gate electrode. Thanks to the higher permittivity of HfAlON, peak transconductance was successfully enhanced up to 3.4 times with an acceptable reliability margin in the state-of-the-art trench SiC MOSFETs by implementing a TiN/HfAlON gate stack.

The Effect of PMA with TiN Gate Electrode on the Formation of Ferroelectric Undoped HfO<sub>2</sub> Directly Deposited on Si(100)

The Effect of PMA with TiN Gate Electrode on the Formation of Ferroelectric Undoped HfO<sub>2</sub> Directly Deposited on Si(100)

Impact of metal gate electrodes on electrical properties of Y2O3/Si0.78Ge0.22 gate stacks

Electrical properties of Y2O3/SiGe metal-oxide-semiconductor (MOS) capacitors with Al, Au, W and TiN gate electrodes have been evaluated in order to study the impact of the metal gate electrodes on Y2O3/SiGe interface properties. It is found that MOS capacitors with TiN gate electrodes can provide better Y2O3/SiGe MOS interfaces than those with Al, Au or and W gate stacks after post metallization annealing (PMA) at each optimized temperature. The physical origins of interface trap density (Dit) reduction are examined from the viewpoint of the composition and the quality of interfacial layers (ILs).

Suppressed charge trapping characteristics of (NH4)2Sx passivated GaN MOS device with atomic layer deposited HfAlOx gate dielectric

The charge trapping behaviors of ammonium poly-sulfide, (NH4)2Sx, passivated GaN MOS device with atomic layer deposited HfAlOx gate dielectric and DC-sputtered TiN gate electrode are investigated and compared with those of GaN MOS device with hydrochloric acid, HCl, passivation. Compared to non-S passivated device, higher peak capacitance (>20% @1MHz), reduced frequency dispersion (~30% ↓), lower hysteresis (~34% ↓), higher breakdown (1.3×), lower stress induced flat-band voltage (VFB) shift (~30% ↓), and lower interface state density (Dit), stronger immunity Dit generation (ΔDit) against gate bias voltage are attained with S-passivated device. Further improved characteristics are observed with post deposition annealing at 400°C for 10min. These behaviors are mainly attributed to higher bond strength energy of SO and SN than those of ClO and ClN bonds.

Poly-Si gate electrodes for AlGaN/GaN HEMT with high reliability and low gate leakage current

AlGaN/GaN HEMT with a BF2-implanted polycrystalline Si gate has been characterized through comparison to TiN gate electrodes. Positive threshold voltage (Vth) shift was observed with the addition of F ions, which in turn degraded the effective electron mobility (μeff) by diffusion into the AlGaN/GaN interface and GaN layer. A large reduction in gate leakage current (Jg) was achieved and the property was maintained even after strong reverse-bias stressing. No additional degradation in μeff was observed, suggesting the formation of a stable poly-Si/AlGaN interface. Therefore, poly-Si gate electrodes have advantages in reducing the Jg and robustness against reverse-bias stressing.

Titanium Silicide/Titanium Nitride Full Metal Gates for Dual-Channel Gate-First CMOS

We demonstrate a thermally stable titanium silicide/titanium nitride (TiSi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub> /TiN) full metal gate (FMG) for dual-channel gate-first high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$k$ </tex-math></inline-formula> /metal gate complementary metal–oxide–semiconductor technology. Unlike prior tungsten-based FMG, the simple TiSi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub> /TiN gate electrode does not require any additional barrier layer preventing oxygen down-diffusion during high-temperature processing, as the TiSi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub> itself blocks oxygen. With HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based gate dielectrics and without any oxygen scavenging scheme, we thus demonstrate a capacitance-equivalent thickness in inversion ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$T_{\mathrm {inv}})$ </tex-math></inline-formula> of 1.11 nm, corresponding to an equivalent oxide thickness of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 0.7$ </tex-math></inline-formula> nm. Silicon channel nFET and silicon germanium channel pFET parametrics are similar to those of control devices utilizing a conventional a-Si/TiN metal-inserted poly-Si stack (MIPS) gate, while providing superior gate sheet resistance. By supplanting MIPS with such an FMG, we anticipate that contacted gate pitch can be scaled aggressively via reduced gate height and borderless source/drain contacts.

Gate Engineering to Improve Effective Resistance of 28-nm High-&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$k$ &lt;/tex-math&gt;&lt;/inline-formula&gt; Metal Gate CMOS Devices

In this paper, we report the development of a high- $k$ /metal gate stacking process to reduce the effective gate resistance, and circuit level validation results in 28-nm gate first integrated high- $k$ /metal gate CMOS devices. To achieve this, millisecond annealing was adopted and the silicon (Si) gate and TiN gate electrode thicknesses were controlled. The recrystallized poly-Si gate by millisecond annealing improved the performance of the ring oscillator (RO) by 15% and the minimum operating voltage ( $V_{\min }$ ) of the high-frequency test pattern (HFTP) by 34 mV. The poly-Si gate improved the uniformity of the boron concentration and suppressed localized low doping area at the bottom of the gate. When the Si gate thickness was reduced by 10 A with respect to the reference (POR) value, the performance of the RO improved by 5% and $V_{\min }$ of HFTP improved by 20 mV due to the shorter boron diffusion distance. A 10- A thicker TiN gate electrode improved $V_{\min }$ of HFTP by 30 mV, since the thicker TiN reduced the TiN/Si gate interface resistance.

Investigation on Oxygen Diffusion in a High-k Metal-Gate Stack for Advanced CMOS Technology by XPS

X-ray photoelectron spectroscopy was used to study the post deposition annealing of a TiN/HfO2/SiO2/Si stack with a HfO2 thickness varying between 2nm and 5nm. Although the annealing was performed in 5N nitrogen, the growth of a SiO2 layer was observed but only in the presence of the TiN layer. It seems that the TiN layer catalyzes the oxidation with oxide anions crossing the HfO2 layer which acts as a solid electrolyte. Oxidation occurs in two steps, a fast one associated to oxide ions coming from the native TiO2 layer on top of the TiN gate-electrode and a slower one associated to the reduction of residual oxygen in the chamber. The system acts similarly to a solid oxide fuel cell between gaseous oxygen and silicon separated by HfO2. The annealing step leaves residual dipoles at the TiN/HfO2 and SiO2/Si interfaces which are the origins of energy shifts between the XPS peaks.

A Study of Sputtered TiN Gate Electrode Etching with Various Wet Chemicals and Post Etch Annealing for Complementary Metal–Oxide–Semiconductor Device Integration Applications

A Study of Sputtered TiN Gate Electrode Etching with Various Wet Chemicals and Post Etch Annealing for Complementary Metal–Oxide–Semiconductor Device Integration Applications

A Study of Sputtered TiN Gate Electrode Etching with Various Wet Chemicals and Post Etch Annealing for Complementary Metal–Oxide–Semiconductor Device Integration Applications

Wet chemicals for etching sputtered TiN metal gate and post etch annealing on HfO2 and HfSiON gate dielectrics were studied with metal–oxide–semiconductor devices. Various wet solutions such as SC1 (NH4/H2O2/H2O= 1:2:5), SPM (H2SO4/H2O2= 10:1), and H2O2 were employed to etch the sputtered TiN. Difference in equivalent oxide thickness (EOT) is negligible among etchants while the lowest leakage current density (Jg) is attained with only SPM solution. Even though SPM treatment shows relative poor surface morphologies compared to H2O2 process, difference in Jg is mainly affected by the amount of absorbed Ti into high-k gate dielectrics during wet etch process. Lower Jg using SPM is attributable to the reduced amount of Ti-adsorption due to additional H2SO4 acid in wet chemical solution, which is confirmed by total reflection X-ray fluorescence. Post etch annealing on high-k layer improves film qualities such as suppressed defects – less frequency dependence – and lowers Jg further while EOT is slightly increased by about 0.2 nm due to SiO2 interfacial regrowth. HfSiON gate dielectric shows stronger immunity against TiN wet etch compared with HfO2. Thus, appropriate etchant and post annealing for the selective TiN etching are carefully considered to suppress defects and Jg for attaining complementary metal–oxide–semiconductor (CMOS) device.

Work function tuning and improved gate dielectric reliability with multilayer graphene as a gate electrode for metal oxide semiconductor field effect device applications

Graphene with varying number of layers is explored as metal gate electrode in metal oxide semiconductor structure by inserting it between the dielectric (SiO2) and contact metal (TiN) and results are compared with TiN gate electrode. We demonstrate an effective work function tuning of gate electrode upto 0.5 eV by varying the number of graphene layers. Inclusion of even 1-3 layers of graphene results in significantly improved dielectric reliability as measured by breakdown characteristics, charge to breakdown, and interface state density. These improvements are attributed to the impermeability of graphene for TiN and hence reduced metallic contamination in the dielectric.

TiN Metal Gate Electrode Thickness Effect on BTI and Dielectric Breakdown in HfSiON-Based MOSFETs

Effects of a TiN gate electrode on interface trap density, bias temperature instability (BTI), and time-dependent dielectric breakdown (TDDB) in HfSiON metal-oxide-semiconductor field-effect transistors are investigated in this paper. Based on experimental data, we found that the TiN metal gate electrode thickness plays an important role in determining the final dielectric stability and the interface quality. Samples with thicker TiN gate electrode, which prevent oxygen diffusion from the high-κ layers toward the α-Si electrode, exhibit a lower Dit level. In addition, the levels of oxygen vacancies are expected to be suppressed by thicker TiN gate electrode, which subsequently alleviates damage at the Si/SiO2 interface and improves both the BTI and TDDB performances.

Detrimental Hf penetration into TiN gate electrode and subsequent degradation in dielectric properties of HfSiO high-k film

Hafnium penetration through the TiN gate electrode as thick as 10 nm is detected in the TiN/HfSiO/SiO2 gate stacks after high-temperature annealing by using x-ray photoelectron spectroscopy. The Hf outdiffusion, showing TiN thickness dependence, is revealed to cause permittivity lowering of the pristine HfSiO high-k layer, which accelerates the equivalent oxide thickness increase and degrades the dielectric properties. In contrast, such diffusion is suppressed by adopting metal inserted polycrystalline silicon stack (MIPS) structure. Our further experiments indicate that the SiO2 regrowth during high-temperature annealing, which is hampered in MIPS structure, triggers the adverse Hf diffusion.