Vertical MOS and tunnel FETs in the same silicon pillar structure with Al and TiN gate electrodes

Abstract

This work presents a silicon pillar structure containing both MOS (Metal-Oxide-Semiconductor) and Tunnel Field Effect Transistors (MOSFETs and TFETs, respectively) with Al and TiN double-gate electrodes. The abrupt n+ regions of drain/source in the p-Si vertical pillar are obtained from sequential 31P+ ion implantations (energies of 100, 50 and 25 keV) and Rapid Thermal Annealing (RTA). The abrupt drain region in the p-Si pillar allows the vertical control of the channel length of the MOSFET device (achieving lengths such as 70 nm) and the formation of a nano-intrinsic region (2 nm), between n+ and p regions, fundamental for the operation of a TFET. The MOSFETs and TFETs, which were fabricated with Al gate, have presented the better results (Ion of 56 μA/μm, gm of 45 μS/μm and (Ion/Ioff) ratio of 107) related to higher performance in conduction regime. However, both devices, fabricated with TiN, have presented higher performance related to leakage and/or off current (Ioff of 1.8 pA/μm). It is important to notice that the alternating use at the same silicon pillar for the both MOSFET or TFET devices can be suitable to the applications in which are necessary high and low power operations, respectively.