Time-to-digital Converter Architecture Research Articles

A 12-bit, 27.8-ps resolution, Anti-PVT variation multi-parallel sampling based coarse-fine TDC for LiDAR sensors

This paper presents a multi-parallel sampling based coarse-fine time-to-digital converter (TDC) with sub-gate delay resolution, large measurement range and high conversion rate for light detection and ranging (LiDAR) sensors. The fine-TDC is designed based on a voltage-controlled delay line (VCDL) but with multi-parallel sampling D flip-flop (DFF) groups to achieve a sub-gate delay resolution based on multi-phase interpolation. These DFF groups are triggered by several successively delayed sampling clocks that generated by a phase-locked loop (PLL) based multi-phase clock generator. The coarse-TDC composed of a coarse counter and a logical control circuit (LCC) is designed to enlarge the measurement range. The LCC is used to calibrate and guarantee the coarse counter neither over-counted nor under-counted. Since the delay of delay units in fine-TDC is also voltage-controlled by another PLL, the resolution of this proposed TDC is robust to process-voltage-temperature (PVT) variation. Besides, this proposed TDC architecture also has the property of dynamic element matching (DEM), which contributes to mitigate the impact of device mismatch and scramble the quantization noise. The post-layout simulations demonstrate a 12-bit, 27.8-ps time resolution, 0.86-LSB DNL, 0.92-LSB INL with 13.6-mW power consumption at 33.3-MS/s under a 1.8-V supply.

A dToF Ranging Sensor with Accurate Photon Detector Measurements for LiDAR Applications.

Direct time-of-flight (dToF) ranging sensors based on single-photon avalanche diodes (SPADs) have been used as a prominent depth-sensing devices. Time-to-digital converters (TDCs) and histogram builders have become the standard for dToF sensors. However, one of the main current issues is the bin width of the histogram, which limits the accuracy of depth without TDC architecture modifications. SPAD-based light detection and ranging (LiDAR) systems require new methods to overcome their inherent drawbacks for accurate 3D ranging. In this work, we report an optimal matched filter to process the raw data of the histogram to obtain high-accuracy depth. This method is performed by feeding the raw data of the histogram into the different matched filters and using the Center-of-Mass (CoM) algorithm for depth extraction. Comparing the measurement results of different matched filters, the filter with the highest depth accuracy can be obtained. Finally, we implemented a dToF system-on-chip (SoC) ranging sensor. The sensor is made of a configurable array of 16 × 16 SPADs, a 940 nm vertical-cavity surface-emitting laser (VCSEL), an integrated VCSEL driver, and an embedded microcontroller unit (MCU) core to implement the best matched filter. To achieve suitably high reliability and low cost, the above-mentioned features are all packaged into one module for ranging. The system resulted in a precision of better than 5 mm within 6 m with 80% reflectance of the target, and had a precision better than 8 mm at a distance within 4 m with 18% reflectance of the target.

Design and Implementation of Two-Stage Time-to-Digital Converter Based on Rapid Single-Flux-Quantum Circuits

This work proposed a new time-to-digital converter (TDC) utilizing rapid single-flux-quantum circuits. The proposed TDC architecture comprises a counter and a ring oscillator to construct a coarse TDC and a vernier delay line to build a fine TDC, which would maintain the high resolution and high dynamic range of the whole TDC. A TDC with the proposed architecture has been designed, fabricated, and successfully tested. The measurement shows that the designed TDC works correctly with a 5.5 ps resolution, a 1320 ps dynamic range, and a 1.5 LSB differential nonlinearity.

A Low-Cost FPGA-Based Coarse-Fine Counting Time-to-Digital Converter With External High-Precision Reference Clock

A new coarse-fine counter time-to-digital converter (TDC) architecture and its implementation techniques for high-precision time-interval measurement are presented. Multi-coarse counters and one fine counter are combined in our TDC architecture. The calibration circuit employs a START and STOP calibration signal generator and a gain calibration circuit. Arbitrarily small time intervals can be measured by distributing the START and STOP signals on different channels. In the implementation process, the high-precision external clock produced by a Silicon Si5338 EVB board and the on-chip high-precision clock are combined to calibrate the TDC output data in real-time. The TDC is implemented on a specially designed FPGA board with a low-cost Xilinx Artix-7 35T FPGA. The measured least significant bit (LSB) is 17.9 ps and the calculated peak-to-peak differential nonlinearity (DNL) and integral nonlinearity (INL) values are 1.006 and 0.920 LSB. The root-mean-square (RMS) resolution is lower than 20 ps in continuous measurement.

Linearity improvement of UltraScale+ FPGA-based time-to-digital converter

Time-to-digital converters (TDCs) based on the tapped delay line (TDL) architecture have been widely used in various applications requiring a precise time measurement. However, the poor uniformity of the propagation delays in the TDL implemented on FPGA leads to bubble error and large nonlinearity of the TDC. The purpose of this study was to develop an advanced TDC architecture capable of minimizing the bubble errors and improving the linearity. To remove the bubble errors, the decimated delay line (DDL) architecture was implemented on the UltraScale + FPGA; meanwhile, to improve the linearity of the TDC, a histogram uniformization (HU) and multi-chain TDL (MCT) methods were developed and implemented on the FPGA. The integral nonlinearities (INLs) and differential nonlinearities (DNLs) of the plain TDCs with the ‘HU method’ (HU TDC) and with ‘both HU and MCT methods’ (HU-MCT TDC) were measured and compared to those of the TDC with ‘DDL alone’ (plain TDC). The linearity of HU-MCT TDC were superior to those of the plain TDC and HU TDC. The experiment results indicated that HU-MCT TDC developed in this study was useful for improving the linearity of the TDC, which allowed for high timing resolution to be achieved.

A Reconfigurable 5-Channel Ring-Oscillator-Based TDC for Direct Time-of-Flight 3D Imaging

Time-correlated single-photon counting (TCSPC) 3D imaging requires the digitization of photon arrival times across an array of single-photon avalanche diodes (SPADs). The most critical performance metrics of time-to-digital converters (TDC) in TCSPC applications are their conversion rate (CR), area, and power consumption. This paper presents a multi-channel RObased TDC architecture whose power consumption scales with its configurable resolution for power-sensitive applications. Further power savings are achieved by sharing one RO among multiple TDC channels. We have demonstrated that sharing one RO among five channels reduces the power consumption by more than 75 relative to non-shared architectures. Here, a 5-channel 12-bit TDC is fabricated in 65 nm CMOS with an area of 1920 um2 per channel. It demonstrates CR up to 125 MHz and offers a resolution configurable over the range of 24-133 ps. At a CR of 125 MHz, the TDC power consumption per channel is 0.1 mW and 1 mW per channel at 133 ps and 24 ps resolution, respectively.

Performance analysis and IP Core Implementation of two high performance time-to-digital converters on Xilinx 7-series FPGA

After extensive research in the past decades, the design of field programmable gate array-based time-to-digital converters (TDC) with tapped delay line (TDL) architecture has become relatively mature, and the performance that can be achieved has also been reasonably high. This paper first presents a comprehensive analysis of measurement uncertainty of two different multi-interpolation TDL based TDCs. By executing multiple time interpolations within one clock cycle, the discrepancy between the resolution improvement and precision improvement is quantitatively analyzed. Therefore, the contributions of major error sources can be clearly understood, which is helpful for TDC designers to predict the performance that their TDCs can achieve. Thanks to the structural characteristics of TDL-TDCs and the build-in function of relatively placed macro (RPM) in Xilinx Vivado Design Suite, the implementations of these two TDCs can be packaged as intellectual property (IP) cores. Since the major building elements and their relative positions can be assigned with pre-established constraints, the high TDC performances can be maintained when the IP cores are instantiated. With the knowledge of TDC architectures and factors affecting performance introduced in this paper, end-users can easily configure the IP cores to meet their requirements without the need of knowing technique details.

Tradeoffs in Time-to-Digital Converter Architectures for Harsh Radiation Environments

Performance degradation of standard time-to-digital converters (TDCs) is inevitable due to the effects of ionizing radiation. In this article, the tradeoffs of different mitigation techniques for TDC architectures are presented. As the effect of radiation is challenging for such high-performance circuits in the state-of-the-art technologies, architectures that can compensate for radiation effects have become a necessity for TDCs to operate in these harsh radiation environments. By looking into the functionality of different architectures focusing on improving radiation tolerance, the main weak and strong points of different TDC architectures, including the compensation circuitry, are described. Possible solutions to those weak points are presented.

A Low-Power Multichannel Time-to-Digital Converter Using All-Digital Nested Delay-Locked Loops With 50-ps Resolution and High Throughput for LiDAR Sensors

This article presents a low-power, all-digital multichannel time-to-digital converter (TDC) for light detection and ranging (LiDAR) sensors. The proposed TDC architecture measures the time interval through a coarse counter, middle, and fine delay line-based interpolation technique (the Nutt method). Automatic calibration by middle and fine all-digital delay-locked loops (ADDLLs) is provided to ensure the stability of the generated time slots. Charge pump, loop filter, and voltage-controlled delay line inside the conventional analog delay-locked loops (DLLs) are replaced by an accumulator (ACC) and digitally controlled delay line (DCDL). This makes the design particularly compact, low power, and suitable for multichannel applications. The presented architecture can generate information for amplitude variation (walk error) compensation. This information is generated by measuring the pulsewidth and position of three successive STOP pulses inside each channel within a single-shot measurement. A low-jitter injection-locked frequency multiplier (ILFM) generates a 625-MHz internal clock signal out of 25-MHz external reference oscillator, which shrinks the number of delay elements to cover one period of the reference clock and improves the precision of the TDC. Operation at higher frequency provides high throughput and short conversion time (less than 3 ns). The three-level TDC offers 13.1- $\mu \text{s}$ maximum input range and 50-ps resolution. The measured DNL and INL of the TDC circuit are 0.47 and 0.71 LSB, respectively. The TDC circuit is implemented in a 180-nm standard CMOS process with a die size of 1.5 mm $\times1.5$ mm. The total power consumption of the multichannel TDC is 87.6 mW.

High-Precision PLL Delay Matrix With Overclocking and Double Data Rate for Accurate FPGA Time-to-Digital Converters

An extremely high-resolution, 2-D Vernier field-programmable gate array (FPGA) time-to-digital converter (TDC) with phase wrapping and averaging has been proposed recently to get an extremely fine resolution of 2.5 ps. However, the cell delays in a delay matrix are not fully controlled so that the TDC performance strongly depends on the stochastic distribution of cell delays, and the input range is limited to less than 20 ns. To achieve both high-precision phase division and wide measurement range, a phase-locked loop (PLL)-based delay matrix, which is capable of overclocking and double data rate (DDR), is proposed in this article. All delay cells are under the precise control of PLLs to generate output phases evenly divided within the reference clock period. For a concept proof, the TDC architecture is implemented on an Altera Stratix-IV FPGA chip to achieve 15.6-ps resolution. The differential nonlinearity (DNL), integral nonlinearity (INL), and rms resolution are measured to be merely −0.157 to 0.137 LSB, −0.176 to 0.184 LSB, and 1.0 LSB, which prove the superiority of the proposed structure to its stochastic counterparts. The proposed high-precision phase division technique can be applied to not only the TDC but also the digital-to-time converter (DTC) to enrich its future applications.

A high resolution time-to-digital-convertor based on a carry-chain and DSP48E1 adders in a 28-nm field-programmable-gate-array.

A field-programmable-gate-array (FPGA) based time-to-digital-converter (TDC), which combines different types of delay chains in a single time measurement channel, is reported in this paper. A new TDC architecture is developed, and both a carry-chain and the DSP48E1 adders, which are integrated inside the FPGA chip, are employed to achieve high resolution time tagging. A single channel TDC has a 3.3 ps averaged bin size, a 5.4 ps single-shot precision, and a maximum sampling rate of 250 MSa/s. The differential-non-linearity of the single TDC channel is -3.3 ps/+24.1 ps, and the integral-non-linearity is within -10.4 ps/+68.6 ps. The TDC performance can be improved by using four TDC channels to measure one input signal, and a 3.4 ps single-shot precision can be obtained. Due to the implementation of the delicated TDC structure, only a small amount of digital resources is required to achieve the picosecond time measurement resolution. Therefore, the reported TDC architecture is suitable for multi-channel applications that require high time resolution measurements of multiple input signals.

Area efficient high-performance time to digital converters

In the digitized world, there is an increased demand for high-speed Time to Digital converters (TDC) in many fields like Nuclear physics, Time of Flight measurements (TOF), Space sciences, medical diagnosis, and imaging. This paper majorly focuses on establishing a Field Programmable Gate Array (FPGA) based Area Efficient and high-performance TDC architectures using KINTEX-7(28 nm) FPGA. Here, we have proposed an area-efficient shift register-based TDC whose output is a thermometer code. Later, this code is passed to an encoder to produce the relative binary code as an output. We have also proposed two encoding techniques, namely Multiplexer (MUX) based encoder with fourth-order bubble error correction and Scalable encoder to generate the output binary code. Our test results using Vivado Design Suite Software have shown that single channel TDC consumes less logical resources with decreased critical path delay and it will be suitable for multichannel architectures. Kintex-7 FPGA has a maximum clock frequency of 450 MHZ, with which we can achieve a resolution of 2.2 ns. To obtain the picoseconds resolution, we can use our TDC in multiple stages, connected in a ring configuration, which can provide fine interpolation and wider dynamic range. In this paper, finally we implemented all the encoders in 180 nm CMOS technologies to estimate the chip layout area and power.

Enhancing Nutt-Based Time-to-Digital Converter Performance With Internal Systematic Averaging

A time-to-digital converter (TDC) often consists of sophisticated, multilevel, subgate delay structures, when time intervals need to be measured precisely. The resolution improvement is rewarding until integral nonlinearity (INL) and random jitter begins to limit the measurement performance. INL can then be minimized with calibration techniques and result postprocessing. The TDC architecture based on a counter and timing signal interpolation (the Nutt method) makes it possible to measure long time intervals precisely. It also offers an effective means of improving precision by averaging. Traditional averaging, however, demands several successive measurements, which increases the measurement time and power consumption. It is shown here that by using several interpolators that are sampled homogeneously over the clock period, the effects of limited resolution, interpolation nonlinearities, and random noise can be markedly reduced. The designed CMOS TDC utilizing internal systematic sampling technique achieves 3.0-ps root mean square (RMS) single-shot precision without any additional calibration or nonlinearity correction.

All-Digital Time-to-Digital Converter Design Methodology Based on Structured Data Paths

Time-to-Digital Converters (TDC) are popular circuits in many applications, where high resolution time measurements are required, for example, in Positron Emission Tomography (PET). Besides its resolution, the TDC's linearity is also an important performance indicator, therefore calibration circuits usually play an important role on TDCs architectures. This paper presents an all-digital TDC implemented using Structured Datapath to reduce the need for calibration circuitry and cells custom design, without compromising the TDC's linearity. The proposed design is fully implementable using a Hardware Description Language (HDL) and enables a complete design flow automation, reducing both development time and system's complexity. The TDC is based on a Delay Locked Loop (DLL) paired with a coarse counter to increase measurement range. The proposed architecture and the design approach have proven to be efficient in developing a high resolution TDC with high linearity. The proposed TDC was implemented in TSMC 0.18 CMOS technology process achieving a resolution of 180ps, with Differential Non-Linearity (DNL) and Integral Non-Linearity (INL) under 0.6 LSB.

A CMOS SPAD Imager with Collision Detection and 128 Dynamically Reallocating TDCs for Single-Photon Counting and 3D Time-of-Flight Imaging.

Per-pixel time-to-digital converter (TDC) architectures have been exploited by single-photon avalanche diode (SPAD) sensors to achieve high photon throughput, but at the expense of fill factor, pixel pitch and readout efficiency. In contrast, TDC sharing architecture usually features high fill factor at small pixel pitch and energy efficient event-driven readout. While the photon throughput is not necessarily lower than that of per-pixel TDC architectures, since the throughput is not only decided by the TDC number but also the readout bandwidth. In this paper, a SPAD sensor with 32 × 32 pixels fabricated with a 180 nm CMOS image sensor technology is presented, where dynamically reallocating TDCs were implemented to achieve the same photon throughput as that of per-pixel TDCs. Each 4 TDCs are shared by 32 pixels via a collision detection bus, which enables a fill factor of 28% with a pixel pitch of 28.5 μm. The TDCs were characterized, obtaining the peak-to-peak differential and integral non-linearity of −0.07/+0.08 LSB and −0.38/+0.75 LSB, respectively. The sensor was demonstrated in a scanning light-detection-and-ranging (LiDAR) system equipped with an ultra-low power laser, achieving depth imaging up to 10 m at 6 frames/s with a resolution of 64 × 64 with 50 lux background light.

A high-linearity time-to-digital converter based on dynamically delay-adjustable looped carry chains on FPGAs.

Time-to-digital converters (TDCs) act as the core component in many scientific and engineering systems which are based on high-accuracy time measurement. Traditionally, field programmable gate array (FPGA) based TDCs are constructed by organizing carry chains in the tapped delay line style, though acquiring high resolution, the differential nonlinearity (DNL) error is high in the range of 2 least significant bits (LSBs)-4 LSBs. Additionally, their long used length of the carry chain costs rather high resource, which is not friendly for multi-channel TDCs. This paper proposes a new TDC architecture based on dynamically delay-adjustable looped carry chains, which works in the Vernier mode. The TDC contains two looped carry chains, and their oscillation period difference (resolution) is dynamically adjusted by a personal computer program without manual intervene and re-compilation of the TDC circuit. A prototype TDC implemented on a Stratix III FPGA obtains the resolution of 26 ps and the DNL less than 1 LSB, but it only uses two carry chains of length of 32 each. The proposed TDC architecture opens a new way to exploit the capability of the carry chains on FPGAs for high-performance TDC applications.

A 16 mW 250 ps Double-Hit-Resolution Input-Sampled Time-to-Digital Converter in 45-nm CMOS

Several new approaches for multi-hit delay-line-based time-to-digital converters (TDCs) are discussed and an input-sampled TDC architecture is realized in 45-nm SOI CMOS. The TDC is characterized by applying a pseudo-random-bit-sequence as an input signal, which consists of multiple time-events/hits. Each low or high transition inside the binary input represents a time-event to be recorded. As the time-event carrying input travels through the delay-line, it generates its delayed phases, which are then sampled by a reference clock with period equal to the delay of the delay-line. The resulting sampled digital word contains a snapshot of all the time-events occurring within one clock period. The TDC achieves a time-resolution of 25 ps and the continuous sampling of the delay-line allows this unique architecture to achieve ideally unlimited dynamic-range. The prototype circuit dissipates 16 mW of power, occupies silicon area of 0.36 mm2, and is capable of detecting two consecutive time-events/transitions at a distance of 250 ps, which is the best double-hit-resolution reported in literature for any TDC.

A 7.4 ps FPGA-Based TDC with a 1024-Unit Measurement Matrix.

In this paper, a high-resolution time-to-digital converter (TDC) based on a field programmable gate array (FPGA) device is proposed and tested. During the implementation, a new architecture of TDC is proposed which consists of a measurement matrix with 1024 units. The utilization of routing resources as the delay elements distinguishes the proposed design from other existing designs, which contributes most to the device insensitivity to variations of temperature and voltage. Experimental results suggest that the measurement resolution is 7.4 ps, and the INL (integral nonlinearity) and DNL (differential nonlinearity) are 11.6 ps and 5.5 ps, which indicates that the proposed TDC offers high performance among the available TDCs. Benefitting from the FPGA platform, the proposed TDC has superiorities in easy implementation, low cost, and short development time.

A High-Linearity, Ring-Oscillator-Based, Vernier Time-to-Digital Converter Utilizing Carry Chains in FPGAs

Time-to-digital converters (TDCs) using dedicated carry chains of field programmable gate arrays (FPGAs) are usually organized in tapped-delay-line type which are intensively researched in recent years. However this method incurs poor differential nonlinearity (DNL) which arises from the inherent uneven bin granularity. This paper proposes a TDC architecture which utilizes the carry chains in a quite different manner in order to alleviate this long-standing problem. Two independent carry chains working as the delay lines for the fine time interpolation are organized in a ring-oscillator-based Vernier style and the time difference between them is finely adjusted by assigning different number of basic delay cells. A specific design flow is described to obtain the desired delay difference. The TDC was implemented on a Stratix III FPGA. Test results show that the obtained resolution is 31 ps and the DNL\INL is in the range of (−0.080 LSB, 0.073 LSB)\(−0.087 LSB, 0.091 LSB). This demonstrates that the proposed architecture greatly improves linearity compared to previous techniques. Additionally the resource cost is rather low which uses only 319 LUTs and 104 registers per TDC channel.

Time-to-Digital Converter Using a Tuned-Delay Line Evaluated in 28-, 40-, and 45-nm FPGAs

This paper proposes a bin-width tuning method for a field-programmable gate array (FPGA)-based delay line for a time-to-digital converter (TDC). Changing the hit transitions and sampling patterns of the carry chain considering delays of the sum and carry-out bins can improve the bin-width uniformity and thus measurement precision. The proposed sampling method was evaluated and compared with the ordinary tapped-delay-line (TDL) method in three different types of FPGAs: Kintex-7, Virtex-6, and Spartan-6. The linearity, equivalent bin width, and measurement precision improved for all the evaluated FPGAs by adopting the proposed method. The measurement precision obtained using the simple TDL architecture is comparable with other complex TDC architectures. In addition, the proposed method improves bin-width uniformity and measurement precision while maintaining the advantages of TDL TDCs, that is, fast conversion rate and small resource usage. Furthermore, the enhanced linearity of the delay line can also improve other carry-chain-based FPGA-TDCs.