Performance analysis and IP Core Implementation of two high performance time-to-digital converters on Xilinx 7-series FPGA

Abstract

After extensive research in the past decades, the design of field programmable gate array-based time-to-digital converters (TDC) with tapped delay line (TDL) architecture has become relatively mature, and the performance that can be achieved has also been reasonably high. This paper first presents a comprehensive analysis of measurement uncertainty of two different multi-interpolation TDL based TDCs. By executing multiple time interpolations within one clock cycle, the discrepancy between the resolution improvement and precision improvement is quantitatively analyzed. Therefore, the contributions of major error sources can be clearly understood, which is helpful for TDC designers to predict the performance that their TDCs can achieve. Thanks to the structural characteristics of TDL-TDCs and the build-in function of relatively placed macro (RPM) in Xilinx Vivado Design Suite, the implementations of these two TDCs can be packaged as intellectual property (IP) cores. Since the major building elements and their relative positions can be assigned with pre-established constraints, the high TDC performances can be maintained when the IP cores are instantiated. With the knowledge of TDC architectures and factors affecting performance introduced in this paper, end-users can easily configure the IP cores to meet their requirements without the need of knowing technique details.