Area efficient high-performance time to digital converters

Abstract

In the digitized world, there is an increased demand for high-speed Time to Digital converters (TDC) in many fields like Nuclear physics, Time of Flight measurements (TOF), Space sciences, medical diagnosis, and imaging. This paper majorly focuses on establishing a Field Programmable Gate Array (FPGA) based Area Efficient and high-performance TDC architectures using KINTEX-7(28 nm) FPGA. Here, we have proposed an area-efficient shift register-based TDC whose output is a thermometer code. Later, this code is passed to an encoder to produce the relative binary code as an output. We have also proposed two encoding techniques, namely Multiplexer (MUX) based encoder with fourth-order bubble error correction and Scalable encoder to generate the output binary code. Our test results using Vivado Design Suite Software have shown that single channel TDC consumes less logical resources with decreased critical path delay and it will be suitable for multichannel architectures. Kintex-7 FPGA has a maximum clock frequency of 450 MHZ, with which we can achieve a resolution of 2.2 ns. To obtain the picoseconds resolution, we can use our TDC in multiple stages, connected in a ring configuration, which can provide fine interpolation and wider dynamic range. In this paper, finally we implemented all the encoders in 180 nm CMOS technologies to estimate the chip layout area and power.